Blog Topics

Design-for-test can no longer be left until the gate level for increasingly sensitive designs aimed at newer processes.

The formal specialist is extending its line for Intel FPGAs that target areas such as AI/ML and HPC, and building out a RISC-V suite focused on ISA compliance.

The company will highlight features within its Trek suite that comply with but then go beyond the capabilities of the Portable Stimulus Standard.

Mentor takes the wraps off new machine learning fueled features in its HLS and physical design families ahead of DAC 2019.

Achronix is introducing an FPGA architecture that pulls a full network-on-chip into the programmable-logic fabric combined with hardened matrix-math processors for AI.

Siemens' new automotive platform commercializes and illustrates the company's ongoing integration of Mentor EDA products within its digital twin concept.

Mentor is active across the program and its main and Verification Academy booths within the exhibition in Las Vegas.

In Las Vegas, the parser specialist will demonstrate its tools for EDA software development across VHDL, SystemVerilog and UPF.

Security and machine learning are two topics that take center stage at DAC this year, says the conference’s general chair Rob Aitken.

Cadence and OneSpin are applying various forms of machine learning to their tools to automate formal verification.