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ES Design West holds its first edition at San Francisco's Moscone Center colocated with SEMICON West in July.

Three hierarchical DFT strategies help cut time-to-market for large AI chips by exploiting regularity and addressing test at the RTL.

Synopsys and GLOBALFOUNDRIES are developing a portfolio of automotive IP for the chipmaker’s 22nm fully depleted silicon-on-insulator (22FDX) process.

Electronic musician Thomas Dolby will be among the keynote speakers at the 56th Design Automation Conference (DAC) in Las Vegas.

An Open Compute Project group working on multichip integration sees a combination of parallel and serial interfaces being important for interchip communication.

Breker CEO Adnan Hamid will lead a tutorial on the Portable Stimulus Standard as part of the verification specialist's activities in Shanghai.

The verification specialist will address the challenges posed by billion-gate SoCs and the integration of formal and simulation in its presentations.

Cadence has launched a web-based EDA service the company hopes will ease the transition from self-hosted computing to more flexible cloud-based development.

RISC-V VIP offerings headline the verification specialist’s presence in Shanghai later this month.

Menta eFPGA IP is highly configurable making it well suited to the evolving designs that exploit HLS abstraction.