IP

Ahead of June's Design Automation Conference, Agnisys and Semifore have both released tools aimed at reducing the overhead of implementing register-rich SoCs.

Oberon Microsystems has ported a set of low-overhead cryptographic codes suitable for Apple's HomeKit to the Cortus APS3RP 32bit processor core.

ARM says it has received test chips designed to check how well an SoC built around a 64bit multicore Cortex v8-A processor complex would work TSMC's upcoming 10nm FinFET process technology.

Cadence Design Systems has increased the throughput of its vision-oriented DSP family to cater for deep-learning applications.

The EDA Consortium is rebranding and extending its activities to better reflect all the tools and services that now comprise IC design.

The 53rd Design Automation Conference has published its program for the upcoming event in Austin, Texas, which will include keynotes from AMD, nVidia, and NXP Semiconductors and tracks that connect electronics to biology.

The DATE 2016 conference saw the launch of a competition to encourage novel designs using MEMS technology.

Open-source hardware, in-field configurability, and a hardware-plus-services approach could protect margins as the IoT hammers down costs, says GSA report.

Mentor Graphics' recent deal with ARM illustrates how proliferation in design is influencing deals between tool and IP vendors.

About 1,600 new UVM System Verilog verification IP memory models will cut testbench development time and offer more time to increase coverage.