IP

May 17, 2014

Cadence ports IP and qualifies tools for 28nm FD-SOI

Cadence Design Systems has developed two sets of IP aimed at the 28nm FD-SOI process developed by STMicroelectronics and qualified tools for the process.
Article  |  Tags: , , , ,   |  Organizations: , ,
April 24, 2014

Altera finds a way to cheaper floating point in FPGAs

Altera has revealed that the DSP blocks in the Arria 10 FPGAs contain the logic needed to make them work as IEEE754-compliant floating-point units.
Article  |  Tags: , , ,   |  Organizations:
April 7, 2014
I heart DAC logo

DAC 2014 offers free exhibit entry for three days

The 51st Design Automation Conference, to be held in San Francisco in early June, is offering free exhibit floor entry for the full three days.
Article  |  Tags:   |  Organizations: , ,
April 4, 2014
Transistors on IDTechEx Printed Electronics 2014 demonstrator

Conference demonstrator brings printed-electronics suppliers together

For its Printed Electronics conference, IDTechEx pulled together a team together with P&G to develop a collaborative demonstration of the technology.
March 20, 2014

ADC design shifts gears for lower power

SAR analog-to-digital converters promise better energy efficiency for a growing range of designs, as S3 Group has found.
Article  |  Tags: , , , , ,   |  Organizations:
February 6, 2014

Cadence to buy Forte and build out HLS offering

EDA giant cites high-level synthesis' move into the mainstream as driven by IP integration challenges in striking deal for the HLS market leader.
November 4, 2013

Rambus CEO calls for collaboration and an architectural focus for memory

Dr Ron Black also discussed his experiences with the Internet of Things in a lively keynote at the GSA Memory+ Conference in Taipei
Article  |  Tags: , , ,   |  Organizations:
October 10, 2013

Cadence launches IP cores for 60GHz wireless and consumer audio

Cadence Design Systems has launched IP cores for high-end mobile audio as well as gigasample ADCs for 28nm to support 60GHz wireless.
Article  |  Tags: , , , , ,   |  Organizations:
October 2, 2013

IP-XACT gets design-flow extensions

Accellera has vendor extensions for IP-XACT that allow tool-specific metadata to be added to support activities such as power-aware verification and floorplanning.
Article  |  Tags: , , , , ,   |  Organizations:
September 9, 2013

SoC design gets hierarchical test strategy, improved compression; system design gains end-to-end IJTAG integration strategy

Synopsys automates standards-based hierarchical test insertion and improves test compression for SoCs; Mentor teams with ScanWorks for system-wide IJTAG.
Article  |  Tags: , , , ,   |  Organizations: , ,

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors