Tensilica vision processor cuts power through memory changes
Memory efficiency has driven the design of the latest video and image processor core developed by Cadence Tensilica.
IP
Vertical structures to debut at IEDM 2015
A novel approach to 3D NAND will be among the presentations at the International Electron Device Meeting to be held in Washington, DC in December.
DVCon Europe initial technical program unveiled
DVCon Europe has published the technical program for its upcoming November conference in Munich, Germany.
IP and software portfolio introduced to speed IoT development
Low-power IP and software portfolio includes security hardware, Bluetooth and ISB interfaces, configurable processors and sensor subsystems
Synopsys extends FPGA-based prototyping to 1.6bn ASIC gates
Synopsys updates its FPGA-based prototyping system to offer more capacity, higher speed, faster bring-up, better ROI
Menta aims for TSMC 28nm with embedded FPGA cores
Menta has launched a family of off-the-shelf IP cores aimed at TSMC’s 28nm processes to provide reconfigurability for SoCs.
USB Type-C IP to ease end users’ frustration
Synopsys delivers reconfigured PHY IP to support reversible USB Type-C connector.
Mediatek extends big.LITTLE strategy with ‘tri-cluster’ smartphone CPU
Ten cores in three clusters help match smartphone power/performance to app load and usage at MediaTek, thanks to Synopsys design exploration tools
SoC verification ‘should use software more’
Verification of SoCs can't be done by adapting IP-level strategies - it'll take a much greater interaction with software, and the use of a shared language
TSMC adds Cadence and Imagination subsystems for IoT
Foundry strikes two more Internet of Things subsystem deals for its 55nm ULP process based on Cadence Tensilica and Imagination MIPS/PowerVR cores.
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