Aachen spinout claims fastest RISC-V simulator

A spinout from RWTH Aachen’s Institute for Communication Technologies and Embedded Systems has developed an instruction-set simulator for RISC-V that it claims to offer higher throughput than available products aimed at software developers.

MachineWare’s SIM-V was designed to make it easier for software developers to test full software stacks – including firmware, operating system kernel and complex user-space applications – at speeds closer to real-time performance as well as to support continuous-integration development environments.

According to Lukas Jünger, managing director and co-founder of MachineWare, the loosely timed simulator can hit around 2000MIPS executing a Dhrystone benchmark on a high-end machine. “We are 2 to 2.5 times faster than QEMU while carrying a complete SystemC TLM simulation with timing annotation,” he added. “Our mission is to equip RISC-V software developers with the tools they need to deliver safe and secure software stacks on schedule and glitch free.”

The simulator is designed to be able to support multiple RISC-V cores in a simulation using SystemC TLM2.0 for interconnection. The company said it will offer tailored versions of SIM-V for different use cases. They include SIM-V Compute, which is intended for running high-end processor cores alongside hardware models of GPUs and PCIe interconnects. SIM-V Edge is optimized for 32bit edge-computing systems, with a greater focus on incorporating connections to a variety of I/O ports.

Both simulators are built on MachineWare’s open-source SystemC modelling library, VCML, and the FTL instruction-set simulator framework, which provides the ability to add custom instruction extensions or define fully custom instruction-set simulators for other microprocessor architectures.