CDNLive Boston to tackle mixed-signal design, host exhibit
Taking place in Chelmsford, MA on 27 August, the conference will feature user-authored papers, tutorials, a designer expo and keynotes from Cadence and IBM.
EDA
Three Accellera proposals aim for better TLM
Three companies have donated technology to Accellera designed to improve TLM 2.0 modeling work, focusing on interrupts, register control and memory maps.
Electrically aware Virtuoso aims to head off physical issues
Cadence Design Systems has rolled out a new version of Virtuoso that deals with the physical-implementation issues that arise in the sub-28nm nodes.
Xilinx tapes out for first of 20nm-generation FPGAs
Xilinx aims to be first of the FPGA makers to produce 20nm devices, expecting to move to production samples for some products by the end of the year.
nVidia to license GPU technology as IP cores
Graphics chipmaker nVidia has said it plans to license as IP cores some of its technology in the hope of building up a customer base among other chipmakers and systems houses developing their own SoCs.
Real Intent highlights hierarchical clock domain crossing with Meridian 5.0
SystemVerilog and Synopsys Verdi integration are among further enhancements as clock domain crossing competition intensifies.
Synopsys launches single kit to optimize IP across PPA
Latest addition to DesignWare portfolio balances trade-offs across CPUs, GPUs and DSPs while automating custom design techniques such as multi-bit flip flops.
Altera outlines process roadmap for ‘Gen 10’ FPGAs
Altera has disclosed a number of the features that will make it into the top end of its upcoming 'Generation 10' family of FPGAs.
FinFET shift could drive analog automation as layout effects bite
The arrival of the finFET brings with it simulation and physical restrictions that might lead teams to resort to layout automation to get the job done.
FinFET processes demand delicate tradeoffs for mobile SoCs – GlobalFoundries process architect
The increasing use of graphics in mobile SoCs means that finFET processes need to be optimised for density and power - as well as early availability at low risk.