EDA

The EDA industry has a way to capture the embedded software market, analyst Gary Smith said ahead of DAC. But it’s not through tools – it’s through models.

The latest revision of the IEEE 1801 Unified Power Format standard for verifying low-power designs has been made available through the IEEE Get Program.

Xilinx and TSMC are forming a single engineering team to accelerate development of a family of finFET-based field programmable gate arrays (FPGAs).

A look at what you can learn about design for manufacturability and yield at this year's Design Automation Conference

Plan around 193nm immersion lithography. Alternatives are years off and not guaranteed, says analyst group

Sessions at the DAC 2013 conference in Austin, Texas focus on low-power design and engineering low-energy systems from the system level down to physical.

DAC 2013's technical program has four sessions on innovation for verification. Some of the hot topics being covered include 3DIC and analog.

Spec-TRACER addresses stringent design reporting demands in safety-critical markets, some of which are moving into the mainstream.

Whether your going to DAC 2013 or not, the EDA analyst's round-up is an invaluable guide to design trends and the tool vendors most actively addressing them.

Cadence Design Systems has launched a timing-signoff tool that uses parallel processing and place-and-route algorithms to try to speed up time to tapeout.