EDA

Leaders from Cadence, Jasper, Mentor and Synopsys are late additions to DAC 2013, giving 15-minute pre-keynote talks previewing design's next half century.

ARM could see shipments of embedded processors based on its architecture begin to outpace its rump market in mobile within four years if growth continues at current levels.

Cadence Design Systems has decided to embrace IEEE 1801, derived from the Unified Power Format (UPF), providing support alongside the Common Power Format (CPF).

Cadence Design Systems has decided to buy Poland-based IP developer Evatronix as part of a plan to round out its portfolio of interfaces for SoC designs.

Cadence-and-Synopsys co-founder and Freescale's new CEO join the DAC 2013 program, while Qualcomm and TI line up to discuss their work in mobile comms as well as taking your questions.

Synopsys users will be gathering at a series of SNUG meetings across Europe over the next month to share insights and experience of using Synopsys tools

It's time to act if you want your semiconductor device or process research to be considered for presentation at IEDM 2013 in Washington DC this December.

DAC 2013 will offer a series of dedicated training courses in SystemVerilog, SystemC, and ARM-based design as well as its regular management day bridging the gap between technology and business.

CDNLive EMEA opens 6 May, providing delegates with an opportunity to find out what their peers are doing with Cadence Design Systems’ tools in real projects.

And then bear in mind that the father of telephony is telling all design engineers a cautionary tale: Documentation. Documentation. Documentation.