Jasper, Duolog bring formal verification to IP specification and assembly, low-power design
Deal creates methodologies and tools to help deliver IP and SoC assemblies verified using formal methods. Low-power verification strategy also launched.
EDA
Timing signoff: maybe it’s time to get rid of the clock
The effort needed in timing signoff could lead to a shift in design towards asynchronous techniques unless advanced OCV technologies improve.
CMOS “good for another century,” says father of finFET
CMOS approaches are likely to underpin electronics for the next century, according to Chenming Hu, father of the finFET
UPF group moves to consider system-power issues
The group that developed the IEEE 1801 Unified Power Format standard is looking to bringing power modeling and estimation to the system level for version 3.0, due in 2015.
Embedded world ‘needs EDA’s models’
The EDA industry has a way to capture the embedded software market, analyst Gary Smith said ahead of DAC. But it’s not through tools – it’s through models.
Latest version of IEEE 1801/UPF available for free
The latest revision of the IEEE 1801 Unified Power Format standard for verifying low-power designs has been made available through the IEEE Get Program.
TSMC and Xilinx forge tighter bonds to speed up finFET port
Xilinx and TSMC are forming a single engineering team to accelerate development of a family of finFET-based field programmable gate arrays (FPGAs).
DAC 2013 Preview IX: Manufacturability
A look at what you can learn about design for manufacturability and yield at this year's Design Automation Conference
Gartner: Multi-patterning here to stay, EUV lithography still 50:50
Plan around 193nm immersion lithography. Alternatives are years off and not guaranteed, says analyst group
DAC 2013 Preview VIII: Low-power design
Sessions at the DAC 2013 conference in Austin, Texas focus on low-power design and engineering low-energy systems from the system level down to physical.