IP-XACT gets design-flow extensions
Accellera has vendor extensions for IP-XACT that allow tool-specific metadata to be added to support activities such as power-aware verification and floorplanning.
EDA
Old problems on a new scale
For the new web TV program Unhinged, Brian Fuller talked to venture capitalist Jim Hogan about the future of mixed-signal and the past of EDA.
SNUG heads to Austin next week
Synopsys user meet in Austin carries forward themes from Boston event.
Intel tips 14nm processor, Quark core and SoC licensing plans
In a keynote at the Intel Developer Forum, CEO Brian Krzanich said the company would start making 14nm processors by the year end and confirmed intel would license SoC designs to be fabbed by other companies.
Speed boost for Palladium emulators
Cadence Design Systems has upgraded its Palladium emulators to a maximum capacity of 2.3 billion gates and 50 per cent higher performance.
SoC design gets hierarchical test strategy, improved compression; system design gains end-to-end IJTAG integration strategy
Synopsys automates standards-based hierarchical test insertion and improves test compression for SoCs; Mentor teams with ScanWorks for system-wide IJTAG.
Imagination gives WiFi better sync for audio
Imagination Technologies has developed an audio synchonization technology for WiFi networks that the company aims to license to consumer-audio chipmakers and OEMs.
SNUG Boston focuses on challenges of gigascale IC design
Meeting focuses on advanced tools and techniques for the rapid development of gigascale ICs.
ARM buys securable display controller
ARM has agreed to buy from Cadence Design Systems the display controller IP cores developed by recent acquisition Evatronix.
IP providers make plans for the internet of things
ARM and Synopsys both plan to make inroads to the internet of things with their IP strategies.