Cadence brings FPGA prototyping and emulation into sync

By Chris Edwards |  No Comments  |  Posted: July 17, 2014
Topics/Categories: Blog - EDA, Embedded  |  Tags: , , ,  | Organizations:

Cadence Design Systems has developed an FPGA-based prototyping system that takes advantage of much closer alignment with its existing Palladium XP emulator to support debugging across both platforms and to reduce the time it takes to bring up designs on the FPGA engine.

Frank Schirrmeister, senior director of product management at Cadence,said the launch of Protium is the latest step in a process to align its system-level development and verification tools, providing a platform more suited to software engineering as the number of hardware bugs reduces.

“Palladium is based on a processor array that offers high [logic] capacity, very good hardware debug, and bring-up times. Rapid prototyping is adjacent to that. As RTL starts to stabilize – where [RTL] updates are only being made on a weekly or monthly basis, it allows you to give a platform to the software developers,” said Schirrmeister. “This is something you can put under your desk but it holds up to 100 million gates. In contrast to emulation you don’t have the advanced debug anymore but it will run faster and you can deliver it to more people for software development as well as offering high throughput for regression testing when you run them overnight. When you find a bug, you can switch back to Palladium. You can reuse a lot of the Palladium environment if you have one, although you don’t need a Palladium to use Protium.”

Faster bring-up times

Schirrmeister claimed bring-up time compared to the previous generation of FPGA-prototyping platforms can be improved four fold. “Bring-up time in FPGA prototyping has been an issue. It could take a matter of months,” he said, pointing to memory capacity as being one roadblock for prototyping platforms.

Cadence has switched from Altera FPGAs to a new generation of Xilinx parts that have higher baseline memory capacity and decided to add more offchip memory as well as the option to include more bulk memory in the form of DIMMs.

“What typically blows the time budget is functional model validation: once the design fits, you have to make sure that the functional model is still doing what you want it to do,” Schirrmeister said. “We have really focused on those steps and reused some of the components that Palladium uses to import the design, do memory support, do the partitioning across FPGAs, and even have Palladium available in the flow to help with debug.

“What’s unique about our approach is that you can take the post-partitioning net list and move it into Palladium, which has a more elegant process for finding bugs.”

Performance tradeoffs

The bring-up phase for Protium lets the user tune the design for performance or opt to get the design onto the FPGAs as quickly as possible, Schirrmeister explained. “There is an automatic flow that involves very little modification of the RTL. It performs clock-tree transformations, partitioning into memories, and place and route. This typically results in a speed of around 3MHz to 10MHz. That’s typically above emulation speeds but on the low end of what software developers would use.

“Then you have manual guidance, which uses constraints to guide partitioning and where you can manually perform the clock-tree simplifications. This can get you into the 10MHz to 20MHz range. This is the range where software designers start getting interested. If you optimize the design on an FPGA-by-FPGA basis and directly connecting memories, then we have seen cases where you can get 100MHz performance.”

The degree to which designs need to be reworked to take RTL changes into account will vary on location. Typically, reused IP would be ‘black boxed’ using the more custom route to improve performance while the integrating logic might have less optimization applied to it on the basis that it will change more often as the project progresses. The compiler can deal with incremental changes, understanding commands to leave certain blocks alone when producing a new partitioning.

As well as launching Protium, Cadence has added support for the IEEE 1801 Unified Power Format (UPF) to its tools alongside the Common Power Format (CPF) that the company has supported for a number of years.

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