Cadence takes Voltus to transistor level

By Chris Edwards |  No Comments  |  Posted: August 5, 2014
Topics/Categories: Blog - EDA  |  Tags: , ,  | Organizations:

Cadence Design Systems has introduced a variant of its Voltus software for power integrity analysis optimized for transistor-level simulations that check for electromigration and IR-drop problems.

Cadence claims the Voltus-Fi tool delivers foundry-certified SPICE-level accuracy in power signoff, using the Spectre Accelerated Parallel Simulator as its simulation core. It complements the Voltus tool launched last year, which is intended for full-chip, cell-level power signoff.

The tool uses a number of techniques, including a patented voltage-based iteration method, which uses less memory and offers lower runtimes compared to traditional current-based iteration method. Voltus-Fi is designed to work with the Quantus QRC Extraction Solution for parasitics analysis and is integrated into the Virtuoso platform.

“The lowest possible power is imperative to customers of our iCE40 and ECP5 FPGA product families, and Voltus-Fi Custom Power Integrity Solution ensures that we achieve exceptionally accurate transistor-level results while minimizing power consumption,” said Sherif Sweha, corporate vice president of research & development at Lattice Semiconductor.

Anirudh Devgan, senior vice president of Cadence’s digital and signoff group said: “Voltus-Fi generates accurate IP-level power-grid models for transistor blocks. This enables customers to then run Voltus IC Power Integrity Solution to achieve complete, full-chip SoC power signoff at top level, which results in the fastest path to design closure.”

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