EDA

At IEDM 2014, CEA-Leti presented a technique that prevents damage to base-layer transistors in monolithic 3DIC processes. As work progresses, the institute is preparing to receive 3DIC designs in 2017.

SystemC coding style can lead to excessive congestion in the logic generated by high-level synthesis. Cadence described how it is attacking the issue at its recent Front-End Design Summit.

The leading EDA analyst also charts growth for RTL and IC CAD in 2014 Market Share Summary, and highlights system-driven shifts in tool evaluation.

The International Electron Device Meeting (IEDM) has once again provided a chance for the major chipmakers to go head-to-head with their latest processes - this time with finFETs.

Cadence has released a tool intended to ease the creation of scenario-driven tests to better exercise complex IP and SoC designs.

In a presentation at the recent ARM TechCon, HiSilicon described the issues in putting together a 16nm finFET-based design built around a cluster of ARM’s Cortex A57 processors.

Canadian startup Invionics has launched a development environment and packager intended to make it easier for users within chipmakers and design houses to build customized tools.

TSMC says it has begun risk production on its FinFET Plus (16FF+) process, claiming that it has reached a greater level of maturity earlier in its development cycle than previous nodes developed at the foundry.

Are we torn between evolution and revolution? Mentor Graphics' Joe Sawicki discusses how pattern matching already in fabs could move up and radically alter the design flow.

Cadence Design Systems has launched an analog simulation tool designed to speed up the characterization of mixed-signal macros that can then be used to create the Liberty representations needed for full-chip signoff.