EDA

March 12, 2015

Cea-Leti opens FD-SOI design center

CEA-Leti has launched a design center called Silicon Impulse with the intention of lowering the entry barrier to using the FD-SOI process.
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March 11, 2015

IoT and RF ‘to drive FD-SOI adoption’

The FD-SOI technology developed by CEA-Leti and STMicroelectronics is beginning to gain ground as chipmakers investigate the process as a way to deliver low-energy, wireless-capable SoCs.
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March 11, 2015

Charting out the roadmap for FD-SOI

As plans crystallize to take FD-SOI down to 10nm, CEA-Leti argues that the technology can provide an alternative path to that of finFETs to get to 7nm processes and beyond.
March 10, 2015

Cadence reworks implementation for both finFET and older processes

Cadence Design Systems has coupled the parallel-processing techniques behind its recently launched sign-off tools to engines intended to deal with sub-28nm process issues in a suite that reworks the company’s key implementation tools.
February 25, 2015

Cadence combines HLS tools in Stratus release

Cadence Design Systems has tied together the Forte Synthesiser and the internally developed C-to-Silicon tools into a new high-level synthesis (HLS) environment the company has titled Stratus.
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February 16, 2015

CDNLive Silicon Valley: last chance for early bird discount

The $99 discount registration price for Cadence's main US user conference will no longer be available after Friday (February 20)
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February 11, 2015

Accellera sets up group for one-stop verification stimulus

Accellera has set up a working group to develop a language-independent way of capturing and managing test stimuli that can be used across a wide range of verification environments.
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February 3, 2015

Speeding up simulation using native System Verilog transactors

Partitioning a verification test bench using native System Verilog transactors can make it easier to move between simulation and emulation.
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January 19, 2015

Ambiq uses subthreshold techniques to cut power on ARM MCUs

Research by the University of Michigan into subthreshold circuit design has led to spinoff company Ambiq Micro creating a family of microcontrollers that it claims provide an ARM Cortex-M4F with power consumption at levels normally associated with an M0+.
January 7, 2015

CEA-Leti deals with heat issue on monolithic 3DIC

At IEDM 2014, CEA-Leti presented a technique that prevents damage to base-layer transistors in monolithic 3DIC processes. As work progresses, the institute is preparing to receive 3DIC designs in 2017.

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