EDA

Designers will need to take crime into account as part of their design signoff process, Wally Rhines argued in his keynote at Mentor Graphics' U2U San Jose 2015 conference.

IoT-themed keynotes from Mentor's Wally Rhines and Qualcomm's Karim Arabi headline vendor's User2User conference on April 21.

The 2015 Design Automation Conference in San Francisco will feature keynotes that focus on body-worn electronics such as Google’s Smart Contact Lens and automotive issues.

Flow draws on existing strengths in Xpedition, Valor, Nimbic and Flotherm among others to optimize 3D design projects and improve cross-disciplinary communication.

Foundry veteran Simon Yang told Semicon China while things are looking up the country cannot count on ‘traditional’ methods or advantages if it's to be a major chipmaker.

CEA-Leti has launched a design center called Silicon Impulse with the intention of lowering the entry barrier to using the FD-SOI process.

The FD-SOI technology developed by CEA-Leti and STMicroelectronics is beginning to gain ground as chipmakers investigate the process as a way to deliver low-energy, wireless-capable SoCs.

As plans crystallize to take FD-SOI down to 10nm, CEA-Leti argues that the technology can provide an alternative path to that of finFETs to get to 7nm processes and beyond.

Cadence Design Systems has coupled the parallel-processing techniques behind its recently launched sign-off tools to engines intended to deal with sub-28nm process issues in a suite that reworks the company’s key implementation tools.

Cadence Design Systems has tied together the Forte Synthesiser and the internally developed C-to-Silicon tools into a new high-level synthesis (HLS) environment the company has titled Stratus.