Research by the University of Michigan into subthreshold circuit design has led to spinoff company Ambiq Micro creating a family of microcontrollers that it claims provide an ARM Cortex-M4F with power consumption at levels normally associated with an M0+.
The Apollo MCUs will contain up to 512Kbyte of flash, supporting both code and data and 64Kbyte of low-leakage SRAM shared between code and data. The company claims to be able to offer active current consumption of 30µA/MHz when operating from flash. A deep-sleep mode which operates a real-time clock from an external crystal consumes just 100nA.
Mike Salas, vice president of marketing, said: “We have a couple of unique characteristics. Because we use subthreshold technology we can optimize both active and sleep-mode power. There’s no need to choose whether to optimize one or the other. With traditional designs, if you want to optimize for sleep, you would choose an older process node with less leakage. For active mode power optimization, you would be more aggressive on process, but at the cost of leakage,” Salas claimed, adding that Ambiq has chosen 90nm as the best node for its current products.
Floating point support
“This is proven technology. We have a real-time clock product on the market today. We can ride the same process curve as everybody else. We just have a lower floor,” he said. “When MCU vendors talk about low power they tend to talk about the M0+. We don’t have to make the same choice. We chose the M4F because it’s a very good solution for wearables, sensors and IoT applications.”
The M4F adds digital signal processing and floating-point instructions to the M-class ARM architecture. Running at 24MHz from a supply voltage of 1.8 to 3.8V, the MCUs contain a pair of buck regulators to supply the lower voltages used across much of the design.
“There are elements of subthreshold and elements of near-and super-threshold where subthreshold behavior is not required. If you looked at the design, you would see a smattering of subthreshold and a whole lot of near-threshold together with a good chunk of super-threshold. The design was a matter of us analyzing at a circuit level what the tradeoffs are and what the performance is,” Salas said.
Blocks such as those dealing with memory tend to be operated at traditional super-threshold voltages because these gain very little from voltage reductions.
Design for subthreshold
“The real special sauce is not so much the ability to dial the voltage down but compensate for all the bad things that happen with subthreshold design,” Salas added.
The bad things include the increased impact of noise and variations in threshold voltage and temperature. As the supply voltage approaches the threshold, not only does the switching speed fall, the impact of differences in that threshold makes it more likely that logic paths will simply fail even though they should work at nominal values. As a result, designs such as those done by Ambiq need circuitry to monitor behavior at runtime or evaluate during test how low a voltage the circuits can tolerate reliably.
“To create this technology there was a real re-imagining of the design flow. We had to come up with new cell libraries and our own flow as well as our own testing fixtures. Traditional testers don’t recognize picoamps. The real secret sauce is in the adaptive circuitry that we’ve had to use to account for variability and to overcome its effects,” Salas claimed.
“We made test chips galore. A lot of that work was done at Michigan to understand what happens at these lower voltages. The standard models don’t simulate these things very well. We are doing things that the textbooks say you shouldn’t do.
As a large contributor to the lifetime energy consumption of a low-power MCU is how much needs to be switched on for it to perform its tasks, Salas said Ambiq has employed similar techniques to those found in similar devices. Although the company has not yet gone into detail on the hardware assistance available to the core in various active and sleep modes, he said the MCUs support peripheral-to-peripheral communications to allow data to be passed between them without waking the core.
Salas said a key feature of the Ambiq design is its 100nA deep-sleep mode, which borrows some technology from the subthreshold real-time clock products to maintain a timing source. The company has not yet published the wakeup time from that state, which does involve reactivating the core clock.