DVCon Europe to examine role of UVM, SystemC in system-level verification
DVCon Europe this year provides a venue for extending UVM, SystemC and TLM for faster, more effective verification its organizing committee claims.
EDA
Creating a reference design flow for 10nm processes: video
Synopsys video details challenges of 10nm design and its collaboration with Samsung Semiconductor to build a full flow to address them.
Cadence building photonics environment around Virtuoso
Cadence is creating a flow that the company believes will make it possible to bring greater predictability to photonics design.
SystemC materials move to Apache 2.0 license
Accellera has moved to an Apache 2.0 open-source license for all of the supplementary materials for its SystemC library.
Chinese dates set for Asia-Pacific editions of Mentor Forum
Wally Rhines headlines as keynote at free technical events set for Shanghai on August 30 and Beijing on September 1.
IEDM alters schedule to keep abreast of process updates
The International Electron Device Meeting has pushed back the deadline for its papers to get the latest developments in process and device design into the December conference.
DTCO points to sub-10nm optimizations
DTCO work by GlobalFoundries and Qualcomm reported at VLSI Symposia shows the need to minimize fin counts in future finFET processes.
RC extraction from ‘virtual fab’ models may speed PDK availability
Electrical analysis facility does RC extraction on virtual fab models, accelerating the availability of early PDKs for new processes
DFT to expand its role for long-term yield
Design for test could look quite different in five years' time compared to the situation designers have today as chipmakers wrestle with the problems of yield control, safety, and aging.
2D tools adapt to create smaller monolithic 3DIC designs
Researchers at the Georgia Institute of Technology adapted conventional 2D layout tools to a two-layer monolithic 3D process that resulted in sizeable space and power savings.