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VLSI 2016
VLSI 2016
June 20, 2016
DTCO points to sub-10nm optimizations
DTCO work by GlobalFoundries and Qualcomm reported at VLSI Symposia shows the need to minimize fin counts in future finFET processes.
Article | Topics:
Blog - EDA
,
Embedded
| Tags:
3nm
,
5nm
,
7nm
,
dark silicon
,
DTCO
,
finFET
,
VLSI 2016
| Organizations:
GlobalFoundries
,
Qualcomm
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