IEDM alters schedule to keep abreast of process updates

By Chris Edwards |  No Comments  |  Posted: July 22, 2016
Topics/Categories: Blog - EDA  |  Tags: , , ,  | Organizations:

The International Electron Device Meeting (IEDM) has pushed back the deadline for its papers to get the latest developments in process and device design into the December conference.

The San Francisco conference to be held on December 3-7, 2016 aims to have a program of some 220 papers with a collection of plenary talks, evening panels and special focus sessions. The submission deadline for the late papers is August 10.

“The industry is moving forward at an accelerated pace to match the increasing complexity of today’s world, and a later submission deadline enables us to shorten the time between when results are achieved in the lab and when they are presented at the IEDM,” said Martin Giles, IEDM 2016 publicity chair and director of transistor technology variation in Intel’s technology and manufacturing group.

The special focus sessions at the conference cover: wearable electronics and the internet of things (IoT); quantum computing; the system-level impact of power devices; and ultrahigh-speed electronics.

The focus on quantum reflects the need to look at the post-Moore’s Law era. The session will explore fabrication issues and will brainstorm R&D directions for new materials, devices, circuits, and manufacturing approaches for the scalable integration of a large number of qubits with CMOS technology, operating at cryogenic temperatures for the realization of quantum computers.

Although the end of Moore’s Law is in sight, there continue to be advances and breakthroughs in ultra-high-speed electronics for communications, security and imaging applications. This special focus session has been organized to discuss, showcase and benchmark advanced ultra-high speed devices and circuits based on high-electron-mobility transistors (HEMTs), heterojunction bipolar transistors (HBTs) and conventional CMOS devices.

The aim of the session on the system-level impact of power devices is to provide a suitable forum for bringing device and circuit experts together to consider impacts at the system level.

The conference will include a full program of tutorials and short courses ahead of the opening of the technical-papers program. They will examine, among other things, the attempts to scale BEOL interconnect in nanometer processes, architectures for neuromorphic computing, reliability issues and spintronics.

Leave a Comment

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors