Fast process access gets Moortec onto 7nm
Early access to tools for new processes is helping Moortec deliver IP to determine the real-time health of on-chip circuits.
EDA
HPC futures report puts acceleration first
A report put together by Europe's HiPEAC high-performance computing research network argues computing is at an architectural turning point
Video series details the physical verification process
Physical verification challenge of large SoCs on leading-edge processes detailed in video series
IEDM shows progress on embedded eMRAM
Embedded magnetic RAM is emerging as a contender for on-chip memory not just from a density standpoint but from that of power.
Leti takes the heat off monolithic 3D
CEA-Leti claimed at IEDM to have achieved major steps in bringing monolithic 3D integration closer to production readiness.
Design Compiler updated for 5nm and beyond
Workhorse synthesis tool updated to make it suitable for use on designs at process nodes of 5nm and below.
Synopsys fuses synthesis and place-and-route to improve IC design quality and time to results
Fusion Compiler uses a single, scalable data model, updated optimization engines, and an analysis backbone based on the industry's golden sign-off tools.
Case study: Achieving earlier signoff convergence and a ‘shift left’ for P&R at Qualcomm
Qualcomm has described its use of Calibre RealTime Digital to enhance its P&R flow.
Accellera updates UVM reference implementation
Accellera has updated the reference implementation for the Universal Verification Methodology to reflect the changes made for the latest release of the standard.
Netronome launches chiplet initiative for network-accelerator SIPs
Data-center networking specialist Netronome has recruited a number of silicon makers and IP suppliers to a standard for chiplet designs that can be used in SIPs for edge computers and servers.
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