Visual timing tool focuses on high-speed PCB signals
Cadence Design Systems has developed a visual timing analyzer for Allegro that tunes signals used by high-speed protocols such as DDR4, PCI Express, and SATA.
EDA
Synopsys targets 5X performance gain with integrated verification suite
New tool technologies, Verdi integration and greater flow concurrency also contribute to a claimed 3X increase in productivity for Verification Compiler.
Real Intent state machine debug focuses on core errors
Real Intent' Ascent IIV tool adds analysis functions to pinpoint fundamental errors in finite state machines and support for SystemVerilog 2009.
IoT calls for security rethink, says Green Hills CTO
The rise of the Internet of Things will drive a change in attitude to security, Green Hills CTO David Kleidermacher claimed in his Embedded World keynote.
Cadence uses SQL to boost verification manager capacity
Cadence Design Systems has launched Incisive vManager, a verification management tool that uses a database backend to manage coverage on large SoC projects.
Synopsys claims latest Design Compiler shrinks existing netlist area, leakage up to 10%
Uses improved logic optimisations and a new approach to meeting timing.
Cadence to buy Forte and build out HLS offering
EDA giant cites high-level synthesis' move into the mainstream as driven by IP integration challenges in striking deal for the HLS market leader.
Cadence updates Incisive with formal, CRV, wreal additions
Cadence's Incisive 13.2 verification environment includes new formal and constraints engines, X propagation checks, and further real-number model support.
Synopsys puts physical IP prototypes into developers’ hands
Synopsys launches HAPS-DX, an FPGA-based IP and subsystem prototyping system, with an optimized toolchain and interoperability with HAPS-70 systems.
Complexity to force shift to four-stage verification
The complexity of on-chip interconnect and the relentless growth in software size will drive the move to a four-stage verification process as well as the increased use of formal techniques to speed up SoC-level testing, Mentor Graphics verification specialist Mark Olen claimed at the Verification Futures conference.