EDA

June 2, 2014

Synopsys uses virtual prototyping kits to kick start IP integration

Synopsys is porting its IP to a series of virtual prototyping kits in a plan to cut the amount of time that it takes to integrate new high-speed interfaces such as USB 3.0
Article  |  Topics: Blog - EDA, Embedded, IP  |  Tags: , , , ,   |  Organizations:
May 29, 2014

Synopsys adds vector DSP operations to ARC EM processor IP

Synopsys has developed a digital signal processing (DSP) instruction set extension to its EM family and two cores that employ it.
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations:
May 29, 2014
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IP takes center stage in push towards systems engineering

At DAC 2014, some 30 per cent of exhibitors are IP suppliers, offering design services or both, demonstrating how system-level design is about building on what has gone before.
Article  |  Topics: Blog - EDA, IP  |  Tags: , ,   |  Organizations: , , , , , ,
May 24, 2014

Real Intent updates lint tool, adds Matlab and Simulink support

More lint rules, better SystemVerilog support, links to MATLAB and Simulink
Article  |  Topics: Product, Verification  |  Tags: , , , , ,   |  Organizations:
May 22, 2014

Mentor seeks component data in PCB design tie-up with Digi-Key

Digi-Key is to sell software developed by Mentor Graphics intended to widen access to PCB design and ease access to vital parts data.
Article  |  Topics: Blog - PCB  |  Tags: , ,   |  Organizations: ,
May 22, 2014

Pulsic opts for “layout early, layout often” strategy

Pulsic has developed an automated mixed-signal layout tool that uses multiple generated variants to let designers pick the best implementation.
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations:
May 21, 2014

Verification perspectives 2: formal for the masses and graph-based techniques

The second part of our interview with Mark Olen and Jim Kenney, looks at how formal and graph-based techniques move the market beyond simulation.
May 20, 2014

Multicore fastSpice extends reach

Cadence has expanded the reach of its parallelized fastSpice engine and Spectre XPS tool to support general-purpose analog and mixed-signal designs.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations: ,
May 20, 2014

Cadence signs with ARM for core optimizations

Cadence Design Systems has signed up for a licence to ARM cores that will let the EDA supplier optimize support for 32bit and 64bit Cortex processors in its tools.
Article  |  Topics: Blog - EDA, Embedded, IP  |  Tags: , , , , ,   |  Organizations: ,
May 17, 2014

Cadence ports IP and qualifies tools for 28nm FD-SOI

Cadence Design Systems has developed two sets of IP aimed at the 28nm FD-SOI process developed by STMicroelectronics and qualified tools for the process.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations: , ,

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