Tabula expects to have 22nm FPGAs next year and is trying to recruit IP developers to an 'app store' for data-center hardware.
National Instruments wants to shift the focus for many embedded systems designers away from hardware cost optimization towards graphical programming as a way of reducing the time it takes to get targets up, running and productive.
Xmos is going back to its roots as a microprocessor architecture designed specifically for low-latency, real-time applications.
Altera has launched the first first SDK to take OpenCL software and target it to FPGAs rather than general-purpose processors or graphics processors.
Expose your transaction-level innovations to the real world early on and catch bugs before simulation.
Blue Pearl is building alliances to bring its timing analysis tools to more users.
French start-up and conference debutant joins the drive to ease partitioning for FPGA prototypes
This newsletter highlights recently-added content on the site that addresses the connected areas of verification, prototyping and emulation. We’ve also added more overview EDA Guides on major design flow challenges.
Xilinx has created Vivado, a new set of tools to support sub-30nm FPGAs that, for advanced designs at least, will take over from its long-established ISE suite.
This looks more like 2.5D silicon interposer-based technology to us, though it is a major and necessary advance
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