DAC 2019 preview: OneSpin Solutions

By TDF Editor |  No Comments  |  Posted: May 28, 2019
Topics/Categories: Blog - EDA, - Verification  |  Tags: , , , ,  | Organizations: ,

OneSpin Solutions recent launches for Intel FPGAs and RISC-V ISA compliance will be at the forefront of its exhibition presence at the Design Automation Conference next month (read more about them here). The company will also be active in DAC’s Designer Track.

DAC 2019 is to take place at the Las Vegas Convention Center from June 2-6. The exhibition runs June 3-5 and OneSpin will be present at Booth #308.

In addition to demonstrations (which can be booked here), staff will be on hand to discuss recent technical papers and research from the company.

Nicolae Tusinschi, product specialist, design verification , will present, “Unbounded Formal Verification of RISC-V CSRs with Interval Property Checking,” during the Designer Track session on “New Frontiers in Formal and Static Verification” (Monday June 3, 10:30am-12:00pm, Room N262).

During the Designer/IP Track Poster Networking Reception, Sasa Stamenkovic, senior field application engineering, will be available to discuss “Advances in Formal Connectivity Checking –– A Case Study on a Multi-Billion-Gate SoC” (Monday June 3, from 5:00pm).

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