emulation

Vendor adds verification support for 25G, 50G and 100G Ethernet through emulator-based virtualization.

Mentor Graphics has released a programming interface to its Veloce emulators intended to support faster and more accurate power estimation.

Partitioning a verification test bench using native System Verilog transactors can make it easier to move between simulation and emulation.

Synopsys is integrating its verification tools to make it easier to move between verification approaches for software centric SoCs

Cadence Design Systems has developed an FPGA-based prototyping system that takes advantage of much closer alignment with its existing Palladium XP emulator to accelerate bring-up and support debugging across both platforms.

Coverage and hardware acceleration can bring greater focus to the SoC-level checks needed to ensure that the final silicon works as expected – both issues tackled in an archived Cadence webinar.

The emulator has become the cornerstone of embedded system level (ESL) design on SoC projects, analyst Gary Smith claimed in a speech ahead of DAC 51.

The second part of our interview with Mark Olen and Jim Kenney, looks at how formal and graph-based techniques move the market beyond simulation.

The first in a series of articles on how various vendors are addressing the flow's most challenging task looks at Mentor's strategy for emulation.

Enterprise Verification Platform adds cross-over SystemVerilog, UVM, and UPF support for Veloce alongside new hardware and software debuggers.