14nm

March 27, 2014

Intel and Altera extend foundry deal into interposer and full 3D

Deal quashes rumors that Altera was about to move its cutting edge production back to TSMC, but nor does it appear to be 'exclusive' for 3D products.
Article  |  Topics: Design to Silicon, Blog - EDA  |  Tags: , , , , ,   |  Organizations: , ,
November 13, 2013

TSMC succession plan emphasizes stability

TSMC stays the course with new co-CEOs as Morris Chang retains executive leadership for now while finFET, 3D and other new technologies settle in.
Article  |  Topics: Commentary, Design to Silicon  |  Tags: , , , , , , , ,   |  Organizations: , , ,
October 4, 2013

Design kit for 10nm FD-SOI due out next year

Research group CEA-Leti expects to have design kits ready for a 10nm FD-SOI process in June 2014
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations: ,
September 11, 2013

Intel tips 14nm processor, Quark core and SoC licensing plans

In a keynote at the Intel Developer Forum, CEO Brian Krzanich said the company would start making 14nm processors by the year end and confirmed intel would license SoC designs to be fabbed by other companies.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , , , ,   |  Organizations:
June 10, 2013

Altera outlines process roadmap for ‘Gen 10’ FPGAs

Altera has disclosed a number of the features that will make it into the top end of its upcoming 'Generation 10' family of FPGAs.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , , ,   |  Organizations: , ,
June 7, 2013

FinFET shift could drive analog automation as layout effects bite

The arrival of the finFET brings with it simulation and physical restrictions that might lead teams to resort to layout automation to get the job done.
June 5, 2013

FinFET processes demand delicate tradeoffs for mobile SoCs – GlobalFoundries process architect

The increasing use of graphics in mobile SoCs means that finFET processes need to be optimised for density and power - as well as early availability at low risk.
Article  |  Topics: Blog - EDA, IP  |  Tags: , ,   |  Organizations:
March 20, 2013

DATE: Double patterning and finFETs force flexibility on tools

EDA companies are having to plan for the different ways in which double patterning and finFETs could move into fabs, Antun Domic of Synopsys explains.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:
March 20, 2013

DATE: Early shift to finFET processes challenges IP development strategies

An early shift to finFET processes is making developing IP libraries more challenging.
Article  |  Topics: Conferences, Blog - EDA, IP  |  Tags: , , , , , ,   |  Organizations:
March 19, 2013

FD-SOI costs to match bulk by year end, says ST

STMicroelectronics pushes on with FDSOI despite dissolution of ST-Ericcson joint venture that provided the lead customer for the process.
Article  |  Topics: Blog Topics, Conferences  |  Tags: , , , , , ,   |  Organizations: ,

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