DAC 2018 preview: Verific
The parser specialist will demonstrate its recently announced INVIO integration to speed development around VHDL and SystemVerilog.
Author Archives: TDF Staff
Case study demonstrates 59% extra power savings for HPC
Taiwanese ASIC specialist Alchip discusses use of Mentor PowerPro for low power on 16nm 24x24 array HPC chip in detail
User2User Silicon Valley rolls out later this month
Mentor's west coast user conference will take place in Santa Clara on May 15. Attendance is free-of-charge.
Combining tools and services for evolving automotive design flows
Automotive companies need to partner closely with tool suppliers as design processes are disrupted by new technologies.
Anne Cirkel recognized for advancing role of women in electronics design
Mentor executive, former Design Automation Conference chair and Tech Design Forum journal founder to receive Marie R. Pistilli Award at DAC 2018.
Free formal verification primer offered by Synopsys
Free e-book offers an introduction to formal verification methods for those who may be curious about the technique, or who need to understand its advantages and limitations in order to manage its use effectively.
Control test point counts for ISO 26262
The automotive safety standard targets 90% in-system test coverage. VersaPoint technology helps to simplify reaching your target.
Leti releases photonics design kit for Synopsys PhoeniX OptoDesigner suite
PDK enables photonics prototyping on MPW runs and compatibility with volume production at STMicroelectronics at Crolles.
Mentor aims to grow emulation with lower gate-count hardware
Strato emulator family adds modular boxes that can build from 640K and 1.25B gate-counts for automotive, mil/aero markets and 'digital twin' strategies.
Layout schema generation speeds early-stage yield learning
LSG generates random design-like test vehicles to enable more detailed pre-ramp analysis for incoming nodes.