Author Archives: Paul Dempsey

About Paul Dempsey

Paul Dempsey is editor-in-chief of Tech Design Forum and has been a technology journalist for 20 years. His work has also appeared in EETimes, Red Herring and specialist journals published by the Financial Times.
April 10, 2013

ProPlus enters simulation with turbo-charged parallel SPICE

The device modeling specialist has integrated its new NanoSpice simulator with existing capture and analysis tools in a broad design-for-yield package.
Article  |  Topics: Blog Topics, Design to Silicon, Verification  |  Tags: , , , , ,   |  Organizations:
April 8, 2013

DAC 2013 Preview II: Panels

FinFETs, ever proliferating verification, 3DIC, security and more feature on our guide to some of the most intriguing panels at DAC 2013.
April 1, 2013

DAC 2013 Preview I: Putting users first and marking 50 years

In the first of our weekly DAC 2013 previews, we discuss program highlights with general chair Yervant Zorian, including an expanded Designer Track, keynotes and golden jubilee celebrations.
March 27, 2013

Are you in the BeagleBone queue yet?

With an April release date promised, we should soon have confirmation on the new processor and price tag for the stripped down embedded Linux development board.
Article  |  Topics: Blog Topics, Blog - Embedded  |  Tags: ,   |  Organizations:
March 27, 2013

Intel and ST stake claims to foundry low power designs

With both now more dependent on foundry business for their finFET (trigate) and FDSOI offerings, DATE was a chance to push their innovations in low power.
March 20, 2013

DATE: The rise of the power architect

Docea Power extends power and thermal analysis tools to address complexity and sub-dividing responsibilities among architects.
Article  |  Topics: Blog Topics, Commentary, Blog - EDA, - ESL/SystemC  |  Tags: , ,   |  Organizations:
March 20, 2013

DATE: The real causes of carbon nanotube FET performance variation

Don't underestimate the influence of metallic nanotubes and tube alignment, say Stanford researchers.
March 19, 2013

SoC prototyping ascends the learning curve

Leading vendors and users spoke of the challenges in developing today's SoCs when faced with a plethora of prototyping techniques - and the challenges that remain.
February 25, 2013

DVCon: UPF and CPF harmony in low power is only a foundation

As DVCon begins, we interview Cadence's Qi Wang, who has led its efforts to converge the Common Power Format with its rival as the IEEE1801 standard is revamped.
Article  |  Topics: Blog Topics, Commentary, Conferences, Blog - EDA, - Standards  |  Tags: , , , ,   |  Organizations:
February 21, 2013

ISSCC 2013: AMD constraints help tame Jaguar

Some conservative decisions were important parts of AMD's design strategy for the 28nm core that's just been specified in PlayStation 4
Article  |  Topics: Blog - EDA, - Verification  |  Tags: , ,   |  Organizations: