TSMC Altera heterogeneous integration is cool but is it 3D?
This looks more like 2.5D silicon interposer-based technology to us, though it is a major and necessary advance
Author Archives: Paul Dempsey
CPTF notebook: The end of planar
It's time for everyone to start thinking about how to handle the incoming finFET age.
Japan one year on: a need to rebuild exposed?
Beyond the earthquake, analyst IHS says the tragedy revealed systemic problems with an aging semiconductor fab base
By the numbers: Penn’s take on WSTS
Future Horizons' Malcolm Penn warns of capacity crunch later this year
CPTF notebook: From restricted to ‘proscriptive’ design rules
Ever increasing lithography challenges mean the next generation of design rules may concentrate on telling you just what you can rather than what you cannot do.
CDN Live: Cadence’s Encounter revamp collates innovation
Performance boost claimed from streamlining optimization across synthesis and layout using modeling, novel CTS strategy and 20nm-ready features.
By the numbers: investment, equipment, sales
We round up the latest headline forecasts and performance data from the Global Semiconductor Alliance (GSA), manufacturers association SEMI and the Semiconductor Industry Association.
TDF Circuits #1: BASIC sets clearer path to healthcare monitoring
Wearable healthcare monitoring systems are a fast growing market, and could surge when clearer device approval regimes are introduced globally. Despite that brake on growth, companies and research organizations continue to innovate in anticipation. The subject of the first TDF Circuits, a graphics-led series looking at innovative implementations, is a subset of the Bio-potential Acquisition […]
Technical Newsletter #1: Common Platform, Samsung, ARM, Cadence
Our first email newsletter previews next month's Common Platform Technology Forum 2012 and features exclusive interviews with senior staff at Samsung, ARM and Cadence Design Systems.
Synopsys verification IP launch has bite
Synopsys has rolled out its SystemVerilog-based verification IP portfolio for a bunch of interconnect standards – and built in support for all the three major verification methodologies.