ISSCC 2013: Energy harvesting needs to prioritize
ISSCC expert panel highlights lowering power over energy sources and identifies the need to focus on the product rather than the technology
Author Archives: Paul Dempsey
Synopsys FPGA prototyping launch puts pragmatism first
HAPS-70 boards launch with latest Xilinx chips, high-speed time-domain multiplexing and Synopsys' take on the debug crunch.
Tektronix aims to slash FPGA prototype debug time
Second generation Certus tool seeks to deliver RTL-level visibility on FPGA boards via a huge boost in signals you can instrument for debug.
ESL must go ‘pay to play’ for growth: Gary Smith
You can now get a complete system-level flow, but bundling 'free' ESL with RTL tools slows the methodology shift, says the leading design analyst. Meanwhile, Cadence moves into the number two vendor slot, but the battle rages on.
Mentor Graphics CEO Wally Rhines – Interview
The Mentor chief discusses ESL-based low power, emulation, 32nm to 20nm and using tools in the cloud.
‘Known unknowns’ and the Cadence take on verification IP
Reviewing some of the sector's main trends with Susan Peterson, group director for VIP at the market leader.
Using verification IP to master AMBA and wider protocol proliferation
How and why Huawei's Hisilicon and DSP specialist CEVA tapped Cadence to implement ARM protocols.
ST aims to seed more interest in FD-SOI
STMicroelectronics offers 28nm process to smaller scale users through CMP and Soitec
Mentor extends Questa with formal coverage checks
New features provide enhanced formal checking analysis, code coverage closure and extended clock domain crossing analysis.
TSMC sketches finFET roadmap
16nm Pathfinder design kits next February and risk production from November 2013. Benchmarked to a 40% increase in speed, 50% reduction in power, and 60% reduction in area.