Author Archives: Paul Dempsey

About Paul Dempsey

Paul Dempsey is editor-in-chief of Tech Design Forum and has been a technology journalist for 20 years. His work has also appeared in EETimes, Red Herring and specialist journals published by the Financial Times.
February 20, 2013

ISSCC 2013: IBM adds digital logic synthesis methodology for System z

The paper on the 32nm upgrade to Big Blue's family of server chips also detailed how the company is tackling BTI.
Article  |  Topics: Conferences  |  Tags: ,   |  Organizations:
February 19, 2013

ISSCC 2013: AMD on how to make a Star Trek holodeck… eventually

Keynoter Lisa Su spun a whimsical idea to serious intent as AMD looks to promote its model for heterogeneous architectures
Article  |  Topics: Blog Topics, Commentary, Conferences, Blog - EDA, Embedded, - General  |  Tags: ,   |  Organizations: ,
February 19, 2013

ISSCC 2013: Energy harvesting needs to prioritize

ISSCC expert panel highlights lowering power over energy sources and identifies the need to focus on the product rather than the technology
Article  |  Topics: Blog Topics, Blog - EDA, Embedded  |  Tags: , ,   |  Organizations:
November 12, 2012

Synopsys FPGA prototyping launch puts pragmatism first

HAPS-70 boards launch with latest Xilinx chips, high-speed time-domain multiplexing and Synopsys' take on the debug crunch.
Article  |  Topics: Blog Topics, Blog - EDA, - Verification  |  Tags:   |  Organizations:
October 30, 2012

Tektronix aims to slash FPGA prototype debug time

Second generation Certus tool seeks to deliver RTL-level visibility on FPGA boards via a huge boost in signals you can instrument for debug.
Article  |  Topics: Blog Topics, Blog - EDA, - General, Verification  |  Tags:   |  Organizations: ,
October 30, 2012

ESL must go ‘pay to play’ for growth: Gary Smith

You can now get a complete system-level flow, but bundling 'free' ESL with RTL tools slows the methodology shift, says the leading design analyst. Meanwhile, Cadence moves into the number two vendor slot, but the battle rages on.
October 26, 2012

Mentor Graphics CEO Wally Rhines – Interview

The Mentor chief discusses ESL-based low power, emulation, 32nm to 20nm and using tools in the cloud.
October 25, 2012

‘Known unknowns’ and the Cadence take on verification IP

Reviewing some of the sector's main trends with Susan Peterson, group director for VIP at the market leader.
Article  |  Topics: Blog Topics, Commentary, Blog - EDA, - Verification  |  Tags:   |  Organizations: , , , ,
October 25, 2012

Using verification IP to master AMBA and wider protocol proliferation

How and why Huawei's Hisilicon and DSP specialist CEVA tapped Cadence to implement ARM protocols.
Article  |  Topics: Blog Topics, Commentary, Blog - EDA, - Standards, Verification  |  Tags: ,   |  Organizations: , , ,
October 18, 2012

ST aims to seed more interest in FD-SOI

STMicroelectronics offers 28nm process to smaller scale users through CMP and Soitec
Article  |  Topics: Blog Topics, Blog - EDA  |  Tags: , ,   |  Organizations: ,