Author Archives: Luke Collins

About Luke Collins

Luke Collins has spent 22 years covering electronics, EDA and innovation. He is a former Editor-in-Chief of Electronics Times in the UK, and co-founded the international IP9x conference series on semiconductor IP. Luke's work has also appeared in The Economist, The Financial Times and Reseach-Technology Management.
May 5, 2015

Xilinx updates Vivado with CDC, faster verification, third-party flows, and lab edition

New version of Vivado adds verification features and speed, extends Zynq support
Article  |  Topics: Product  |  Tags: ,   |  Organizations: , , , ,
April 30, 2015

Safety compliance in hardware and software development focus of online/Munich conference

Online and physical conference focuses on achieving compliance with safety standards such as ISO26262, DO254, and DO178
Article  |  Topics: Blog Topics, Conferences, Standards, Verification  |  Tags: , , , , ,   |  Organizations: ,
March 10, 2015

Synopsys claims finFET leadership

Synopsys claims its tools have enabled 90% of finFET designs currently going into volume production
Article  |  Topics: Product  |  Tags:   |  Organizations: ,
February 3, 2015

Speeding up simulation using native System Verilog transactors

Partitioning a verification test bench using native System Verilog transactors can make it easier to move between simulation and emulation.
Article  |  Topics: Blog - EDA, - Verification  |  Tags: , , , ,   |  Organizations:
October 28, 2014

10Gbit/s USB 3.1 IP and verification support on the way

USB 3.1 IP, verification IP, virtual development kit build on Synopsys' USB 3.0 DesignWare and supporting ecosystem
Article  |  Topics: Blog - IP, - Verification  |  Tags: , , , ,
October 28, 2014

imec and Coventor partner for 7nm process development

Process development alliance will enable Imec to experiment on 10 and 7nm processes in the computer before moving to the fab
Article  |  Topics: Design to Silicon  |  Tags: , , , ,   |  Organizations: ,
October 24, 2014

Synopsys combines cell-aware, slack-based test to find transient defects, adds eFlash support

Two approaches to greater reliability revealed in Synopsys ATPG and DesignWare updates
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
October 14, 2014

ARC core focuses on embedded Linux applications

Synopsys updates ARC core to improve support for embedded Linux and other advanced operating systems such as Android
Article  |  Topics: Blog - IP, - Product  |  Tags: , , , ,   |  Organizations:
October 8, 2014

Still time to get to European design and verification conference

DVCon Europe brings design and verification insights to Munich next week.
October 7, 2014

Minimal 32bit IP cores tackle connected devices market

Minimal IP cores are meant to serve broader market than IoT, using revised instruction set to increase code density, save on chip memory and enable security
Article  |  Topics: Blog - IP  |  Tags: , , , , ,   |  Organizations: