DAC 2018 preview: Synopsys
DAC 2018 will see Synopsys focusing on close links with foundry partners, as well as exploring ways to exploit the potential of machine learning, in both SoC architectures and SoC design flows.
Author Archives: Luke Collins
Synopsys speeds PrimeTime with AI
Synopsys applies AI to speed PrimeTIme, as part of wider strategy to exploit machine learning to ease chip design
Synopsys offers ASIL D ready embedded vision IP for ADAS and autonomous vehicle SoCs
Synopsys has extended its range of semiconductor IP for use in advanced driver assistance (ADAS) and autonomous vehicle SoCs with the launch of embedded vision processor blocks that have been given safety enhancements.
TSMC certifies Synopsys tool flow for 7nm EUV process
New flow enables high-performance, high-integration designs.
Synopsys UFS 3.0 IP doubles bandwidth to flash
Faster, lower power flash interface IP with built-in encryption/decryption speeds access to embedded and removable storage.
Formal focus for Synopsys blog
Synopsys experts are now blogging about key issues in formal verification - how to use it, which techniques to apply, and the effort/reward ratio of doing so.
DAC 2017 preview: Synopsys
Synopsys has released details on its varied activities at DAC 2017, ranging from panels to technical papers.
Designing for autonomous vehicles
Two upcoming webinars focus on key aspects of designing the kinds of advanced driver assistance systems (ADAS) that will pave the way for fully autonomous vehicles.
Five steps to faster FPGA implementation
Five steps you can take to speed up the FPGA implementation of a complex design, from structuring your design flow to debugging its output.
Speeding up AMS design in the age of finFETs
STMicroelectronics, Samsung, GSI Technology and Synopsys talk about the challenges of doing AMS design on finFET processes.