DAC 2012: Calypto brings tools together for high-level power savings
Calypto has combined the Catapult high-level synthesis (HLS) tool with elements of its PowerPro software to focus on the demand for lower-power SoC designs.
Author Archives: Chris Edwards
TI tool hands out low-power tips
Texas Instruments has put together a tool aimed at users of its MSP430 microcontroller family that will help cut the power consumption of their applications.
Analog designers ‘need to use digital tools’
Designers working on mixed-signal circuits will benefit from using digital tools, Cadence's SVP of R&D for custom design said at CDNLive EMEA today. But for those who don't a faster fast Spice is on its way.
Intel’s tapered fin reveals short-channel issues
A startup has analyzed the shape of Intel's fins and found the process is not quite as well-behaved as circuit designers would perhaps like.
Mentor unveils second-generation Veloce emulator
Mentor Graphics has updated its Veloce emulator, using a newly developed chip to double capacity while, at the same time, developing new software to overcome the traditional handicaps of in-circuit emulation.
Xilinx revamps design software for new processes
Xilinx has created Vivado, a new set of tools to support sub-30nm FPGAs that, for advanced designs at least, will take over from its long-established ISE suite.
SpringSoft tackles analog automation with new twist on constraints
SpringSoft is trying a different approach to constraint-based design in a bid to improve the automation of custom and mixed-signal design, particularly on advanced process nodes.
U2U to assess state of 3DIC flow
Qualcomm's director of engineering is among the panelists at the upcoming U2U event in Santa Clara who will look at the state of play for 3DICs and how design flows are bearing up to dealing with 3D integration.
Synopsys builds 3D into tool portfolio
At the SNUG event this week, Synopsys is taking the wraps off its plans to support 3DIC, with updates to tools for physical design and verification.
DATE notebook: Aldec builds in more support for VHDL methodology
Aldec has updated its Riviera Pro tool to provide more support for OS-VVM, the recently launched verification methodology for VHDL