SpringSoft tackles analog automation with new twist on constraints

By Chris Edwards |  No Comments  |  Posted: April 17, 2012
Topics/Categories: Design to Silicon, Blog - EDA  |  Tags: , , , , ,  | Organizations:

Anyone who attended the analog-design panel in the DATE Exhibition Theatre last month would hav left with the impression that constraint-based design was not the way to go – successive attempts to introduce it have met with failure. SpringSoft’s decision to have another go at using constraints to automate circuit layout looks a bit strange in this context. But the company believes it has addressed the biggest stumbling blocks to its adoption.

Dave Reed, senior director of marketing at SpringSoft, said the core of the new Laker custom and analog design tool is a focus on analog prototyping: taking schematics and using automated layout techniques to gauge how well a design is going to work. This, he said, is driven by the way proximity effects come into play in sub-50nm nodes. How close a transistor lies to the edge of a well or to another device can significantly change key parameters such as threshold voltage and transconductance. So, topologies that work well in one process and, indeed, on another part of the chip, may not work so well in a new location.

“At the schematic level, I have no idea if an element will be close to the edge of a well. So you can use layout exploration to get an idea of how the circuit will behave,” said Reed.

The problem is getting even a prototype of a layout done quickly. If you have a constraint-driven flow, you can use rules to determine how placements are driven by considerations such as proximity to a well boundary. “The key problem is how do you generate the constraints in the first place that tell the tool what to do? Customers have not wanted to spend a lot of time in defining constraints. So we have been working on a way to define them automatically.”

The latest release of the tool contains code that attempts to identify common subcircuits such as voltage references, cascode pairs and current mirrors. “There are 20-plus structures that we have taught it,” said Reed, adding that it will recognize logic structures such as NOR gates as well.

Some of the panelists at DATE talked about the tedium of dealing with common subcircuit elements such as these and how they detract from the effort needed for new elements that need the attention of an expert circuit designer. Something that automates the placement of subcircuits that offer little scope for differentiation may be what is needed for constraint-driven design to become accepted.

The move beyond 30nm has called for further changes in Laker. Mark Milligan, vice president of corporate marketing, said: “We have created a new DRC engine that is capable of understanding 20nm rules. You have to push the understanding of the design rules into the design process.”

The new DRC engine is not meant to replace the live link that the company built to Mentor Graphics’ Calibre – an external DRC tool remains the preferred route for sign-off level checks. The internal engine is meant to guide the designer as to what makes sense in a custom layout or cell design. Although design rules are far more restrictive than ever, the element that has pushed the need for constant design-rule analysis is double patterning.

Because the separation into masks is a graph colouring problem, and you generally only have two colours to play with, knowing whether a given juxtaposition of features is viable is essential.

“We color as a way of checking whether the final coloring is possible,” says Reed, adding that although there is still a debate over whether coloring will be done by custom and cell designers or handled automatically by tools, the trend seems to be towards putting that control in their hands. ” We have to make sure that the colouring is possible.”

Having embraced the Open Access database in recent releases of its tools, SpringSoft has made some changes to improve speed.

Reed explained: “Although the CPUs themselves have been getting faster, there has been a comparative slowdown related to disk I/O. There is less local storage: more of it is off in a computer room somewhere. We looked at how we could minimize disk accesses. the part of the Open Access database that talks to files is a plug-in — you are allowed to rewrite. So we did and achieved a two to ten times speed-up,” said Reed.

The difference is experienced when reading and writing designs out from the in-memory database but also during tool operations. “We found that with some things Open Access was going to disk when it didn’t need to. Even redrawing the screen involved a number of disk accesses,” Reed added.

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