U2U to assess state of 3DIC flow

By Chris Edwards |  No Comments  |  Posted: April 5, 2012
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One of the themes at Mentor’s U2U event in Santa Clara later this month is that of the 3DIC. A panel session will ask whether the vaunted benefits of the 3DIC are realisable. Among the people sitting on the panel is Riko Radojcic, director of engineering at Qualcomm, who has done a lot of work on the 3D integration of processors and memory.

At the Design Automation Conference (DAC) last year, Radojcic said Qualcomm is attracted to the idea of putting memory on top of processors because of the form factor but also for speed. “We think 3D is inevitable especially for bandwidth. It is becomeing increasingly difficult to provide the bandwidth [with conventional packaging]. You can only increase the clock speed so far. Wide I/O is inevitable.”

He added: “It’s hard to have thousand interconnects with a wirebond solution.”

One way to get a lot of I/O lines from memory to the processor is to stack the components and use TSVs to provide the connections from the top surface of the processor to the memory, possibly using an interposer to provide a way to split I/O between the memory cube and external pins. This makes it possible

“One day I will be able to say I told you so,” said Radocjic. “There is a lot of FUD. A lot of us went off and looked at various issues. But it seems OK. 3D takes the pressure off package design. So it really extends the BGA technology.”

Also on the panel are Professor Paul Franzon of North Carolina State University, Ruebin Fuentes, senior director of Amkor Technology’s package design center and Matthew Hogan, Calibre technical engineer at Mentor Graphics. They will, together with Radojcic, look at the necessary elements needed in the design flow and whether any are missing.

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