Foundation plans virtual ISA for heterogeneous systems
Six companies have come together to launch a foundation intended to develop standards for software that can run on a wide variety of computers based on a heterogeneous mix of processors.
Author Archives: Chris Edwards
From devices to systems: Intel’s projections for the future
In his opening keynote at the VLSI Technology Symposium on Tuesday, Intel director of components research Mike Mayberry provided four ways to look into what is from today's perspective a very foggy future.
Doping gives finFETs threshold control
You want finFETs with different threshold voltages on the same SoC? Forget what the FD-SOI guys tell you: it's possible. At least with a certain amount of performance loss, say IBM and GlobalFoundries.
Rethought analog design focuses on event-driven simulation
During his CEDA talk at DAC last week Professor Mark Horowitz challenged the audience to find holes in the approach he and his team have been developing over the past few years to rethink analog design.
Degrees of freedom for finFETs
FinFET or trigate structure provide a number of degrees of freedom in design in the battle against DIBL – and one of those dimensions is doping, Professor Tsu-Jae King Liu explained in a course ahead of the 2012 VLSI Symposia this week.
FD-SOI to get foundry push in ST deal
A deal between GlobalFoundries and STMicroelectronics has answered the question as to where ICs based on an FD-SOI process can be made, and not just for ST.
DAC 2012: A look inside Accellera’s UCIS
Accellera has approved version 1.0 of the Unified Coverage Interoperability Standard (UCIS). Here's how it works.
DAC 2012: Intel’s Ivy Bridge chip chop shop
Intel's Ivy Bridge series of processors were designed from the outset to be split apart and recombined to create variants of the base platform, Intel architecture project manager Brad Heaney explained during the Wednesday keynote session at DAC 2012.
DAC 2012: ARM tips subthreshold power-gating technique
Could subthreshold circuitry help extend the reach of power gating? Mike Muller said during his DAC keynote that the technique looks viable.
DAC 2012: Avoid IP getting lost in translation
Do you know where the IP for your design has been? Or where it's going? That's the question a lot of CAD groups face as they struggle with regulatory, bug-fixing and yield issues.