Intel’s tapered fin reveals short-channel issues

Even before the official launch Chipworks had samples of Intel’s first foray into finFETs – or trigate transistors – in the shape of the Ivy Bridge processors. So, on 23 April, the reverse-engineering specialist released cross-sections and other images of the new processors as part of its analysis.

One notable feature was that, although Intel is careful not to use the word ‘fin’ in combination with ‘FET’, the profile of the channel is not unlike that of a fin in the natural world – tapering as it nears the top. It raised the question: is this what Intel wanted or is what is possible using current manufacturing techniques?

Gold Standard Simulations, a startup specialising in nanometre-scale simulation that has formed out work in Professor Asen Asenov’s group at the University of Glasgow, has released results of simulations that tend to point to the latter. You probably don’t really want a fin shaped like this but, if that’s what you have, it will work, just not as well as you would like.

The problem with the tapered fin, according to GSS, is that it tends to force carriers to the narrowest part at the top at higher voltages. This leads to a very high, focused current density, which may affect long-term reliability.

The taper also changes the dependence of threshold voltage on gate length as the current at low voltages moves down the fin towards the heavily doped region designed to stop carriers moving into the bulk silicon. As the fin thickens, the gate begins to lose its control, with the result that the tapered fin is not quite so good on short-channel effects as the ideal rectangular fin. That is probably not great news for Intel as it tries to move into mobile devices but, if these fins have the same overall performance as the graphs shown last year of the trigate versus regular CMOS, it should give the chip giant a sizeable advantage in low-power performance.