For traditional users of programmable logic, Xilinx’s revamp of the design software intended to go with its sub-30nm products represents a big step away from a conventional FPGA flow. For ASIC designers, there is a lot that will be familiar in the approach that Xilinx has taken, although the company is taking advantage of its leading position in terms of design seats to try to drive the adoption of system-level design and the IP Xact set of standards.
Introducing the Vivado software, Tom Feist, senior marketing director for design methodology at Xilinx, said: “Four years ago we said we needed to invest in a next-generation design suite. Our current suite, ISE, is about 15 years old. But times have changed. The FPGAs and programmable devices have become much more complex. Xilinx has moved from being just a programmable-logic vendor to what we call ‘all programmable’.”
Feist said the company sees IP reuse as crucial to cut the time it takes to put multi-million gate FPGA designs into production, something of which ASIC designers are only too aware. However, the plan is to move at least some of the IP reuse on the system level. “We are focusing not just on RTL but algorithmic-level design,” said Feist.
It’s not in the standard version of the suite, but Xilinx is using its acquisition of AutoESL to provide synthesis from the algorithmic level. The other strand to Xilinx’s plans for IP reuse are centered on IP-Xact. “It doesn’t provide a lot for the end user directly but it does help automate flows,” said Feist.
As well as being used to package the Xilinx-supplied IP cores, the IP-Xact tools can be used to take parameterizable customer-defined cores and package them as well. “We use the IP-Xact metadata to define the interfaces so that the blocks can be stitched together using just one line of code,” Feist explained.
IP synthesized from the algorithmic level is also put through the packaging system. “It automatically performs interface synthesis so you can stitch the blocks together very rapidly,” said Feist.
Similar to the change in ASIC synthesis towards physically aware synthesis, Xilinx has rewritten its core implementation tools to focus on the problems of wire length and congestion. The company has found that, even with the buffered array structure of an FPGA, long wires are troublesome and tend to increase congestion. So the company has moved away from good old simulated annealing to an architecture that allows more efficient handling of placement.
Also like the ASIC flows in place now, Xilinx has adopted a standard database format. But it is one of Xilinx’s own design rather than a standard such as Open Access. “We used standards where we could. We support Synopsys design constraints [SDC] and Tcl. But the data model had to be optimized for our needs. In the ASIC world, everything is fine-grained. But the FPGA is a coarse-grained architecture.”
The company looked at obtaining an OEM version of a mixed-language simulator to support designs that use SystemVerilog and VHDL code but opted to implement its own. “We looked externally but none of the suppliers wanted to do it,” said Feist.