Author Archives: Chris Edwards

About Chris Edwards

Chris Edwards has spent a long time covering electronics and EDA. He is a former Editor-in-Chief of Electronic Engineering Times UK and electronics editor of the IET's Engineering & Technology. His work has appeared in a variety of international newspapers including The Guardian, The Daily Telegraph, The Age and the South China Morning Post.
May 9, 2018

Motion harvester wins MEMS design contest

Energy harvesting, mechanical reprogrammable logic, and genetic algorithms were among the finalists for the MEMS design competition.
May 8, 2018

Cadence opens three fronts on mixed-signal failures

Cadence has started the rollout of a set of design tools for mixed-signal reliability analysis.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
May 4, 2018

7nm process with EUV to feature at VLSI

Samsung Electronics will describe at the upcoming VLSI Symposia how its engineers have applied EUV to a variety of layers in a 7nm finFET process.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations: , , ,
May 2, 2018

Arm adds tamper resistance to M-series core

Arm aims to bring protection against physical tampering and side-channel attacks into processor cores designed for IoT nodes, starting with one of its M-series designs.
Article  |  Topics: Blog - IP  |  Tags: , , ,   |  Organizations:
May 1, 2018

Andes teams with Imperas and UltrasoC for RISC-V

Andes Technology has expanded support for its RISC-V processor cores through deals with Imperas and UltraSoC.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations: , ,
April 11, 2018

Tensilica DSP extends pipeline for performance

Cadence Design Systems’ Tensilica division has launched a variant of its Vision P6 processor core to tackle embedded designs that need to run a mixture of imaging and deep learning-type algorithms.
Article  |  Topics: Blog - IP  |  Tags: , , , ,   |  Organizations:
April 10, 2018

Cadence tunes Virtuoso for 5nm and SIP

Cadence Design Systems has made enhancements to its Virtuoso mixed-signal layout tool at both the system-level and nanometer-design levels for its 18.1 release.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , , ,   |  Organizations:
April 9, 2018

DAC keynotes and sessions aim for AI

DAC in June will feature a series of keynotes and technical sessions on machine learning and AI for both target applications and in the design process itself.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , , ,   |  Organizations: , , ,
March 21, 2018

VLSI Symposia adds day for AI

June's Symposia on VLSI Technology & Circuits will bring together a number of industry trends that extend from implantable biomedical applications to machine learning and cloud computing under the banner of technologies for ‘smart living’.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations:
March 19, 2018

Xilinx plans reconfigurable compute for 7nm FPGA generation

Xilinx plans to make reconfigurable computing the focus of its upcoming generation of FPGAs, which will be made on a 7nm finFET process at TSMC and expected to start sampling next year.
Article  |  Topics: Blog - Embedded, IP  |  Tags: , , , ,   |  Organizations: