Verification

November 12, 2015

DVCon Europe: Getting TLM to cope with proliferating ECUs and serial protocols

High powered alliance develops TLM standards to address growing automotive and IoT concerns.
October 19, 2015

Mentor targets next-gen Ethernet with emulation

Vendor adds verification support for 25G, 50G and 100G Ethernet through emulator-based virtualization.
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September 16, 2015

Synopsys extends FPGA-based prototyping to 1.6bn ASIC gates

Synopsys updates its FPGA-based prototyping system to offer more capacity, higher speed, faster bring-up, better ROI
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June 24, 2015

Mediatek extends big.LITTLE strategy with ‘tri-cluster’ smartphone CPU

Ten cores in three clusters help match smartphone power/performance to app load and usage at MediaTek, thanks to Synopsys design exploration tools
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June 8, 2015

Synopsys to acquire Atrenta

Atrenta's SpyGlass line and others to be absorbed in Verification Continuum and Galaxy as part of EDA's latest major consolidation.
June 7, 2015

DAC 2015 forecast: Cloudy with a chance of Spice installs

Spice regressions, library characterisation and yield analysis are all being promoted as suitable for running on the cloud
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May 21, 2015

Real Intent tackles CDC at the physical level

Meridian Physical CDC targets post-synthesis gate-level clock domain crossing issues, including unintended glitches and functional failures.
May 11, 2015

Formal verification conference offers ARM, Broadcom, Imagination insights, online access

Conference addresses formal verification techniques at levels to suit beginners through to experts
April 30, 2015

Safety compliance in hardware and software development focus of online/Munich conference

Online and physical conference focuses on achieving compliance with safety standards such as ISO26262, DO254, and DO178
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February 25, 2015

Real Intent updates linter for aviation, Mathworks and SystemVerilog

Ascent Lint adds checks for DO-254, tighter integration with HDL Coder, more SystemVerilog support and new VHDL and Verilog rules in March update.

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