DAC 2012: Synopsys marries virtual and FPGA prototyping
Expose your transaction-level innovations to the real world early on and catch bugs before simulation.
Verification
DAC 2012: A look inside Accellera’s UCIS
Accellera has approved version 1.0 of the Unified Coverage Interoperability Standard (UCIS). Here's how it works.
DAC 2012: Introducing Flexras Technologies
French start-up and conference debutant joins the drive to ease partitioning for FPGA prototypes
DAC 2012: Accellera takes first step to a real coverage standard
UCIS 1.0 will provide a common format to analyze and compare data from different vendors' tools. Yup, it's a 'Biden' of a deal.
Technical Newsletter #4: Verification, Emulation, Prototyping
This newsletter highlights recently-added content on the site that addresses the connected areas of verification, prototyping and emulation. We’ve also added more overview EDA Guides on major design flow challenges.
Synopsys builds 3D into tool portfolio
At the SNUG event this week, Synopsys is taking the wraps off its plans to support 3DIC, with updates to tools for physical design and verification.
Synopsys verification IP launch has bite
Synopsys has rolled out its SystemVerilog-based verification IP portfolio for a bunch of interconnect standards – and built in support for all the three major verification methodologies.