Speeding up simulation using native System Verilog transactors
Partitioning a verification test bench using native System Verilog transactors can make it easier to move between simulation and emulation.
Verification
Gary Smith EDA: PCB ‘a door to the future’ but ‘slow take-off’ for ESL
The leading EDA analyst also charts growth for RTL and IC CAD in 2014 Market Share Summary, and highlights system-driven shifts in tool evaluation.
10Gbit/s USB 3.1 IP and verification support on the way
USB 3.1 IP, verification IP, virtual development kit build on Synopsys' USB 3.0 DesignWare and supporting ecosystem
Real Intent’s Meridian CDC flexes hierarchical muscle, adds flexible debug
Major overhaul of clock domain crossing suite adds configurable debugger, boosts performance by 30% and cuts memory 40% for 'giga-scale' designs.
Verification platform offers unified compile, debug environments
Synopsys is integrating its verification tools to make it easier to move between verification approaches for software centric SoCs
DVCon Europe focuses on systems design and verification
Focus on systemic issues matches DVCon Europe event to European interests
Real Intent puts the accent on debug with new Ascent IIV release
More than 20 new features and improvements are added to the static functional tool.
Synopsys adds formal, CDC, low-power checks to Verification Compiler
Synopsys adds formal, static, clock-domain crossing, and low-power checking to verification engineers' toolbar
Real Intent’s Pranav Ashar on converging design and verification
Verify early and simulate as little as possible - the idea is familiar but how do you get there?
Mentor’s Wally Rhines on tools as a cultural issue
Whether you're going to DAC this week or not, it's worth remembering one of the other key factors that will inform your judgments on new tools.
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