June 18, 2013
SystemVerilog and Synopsys Verdi integration are among further enhancements as clock domain crossing competition intensifies.
June 17, 2013
Incremental formal verification of ECOs makes finalisation of chip design process faster, more predictable.
June 5, 2013
Deal creates methodologies and tools to help deliver IP and SoC assemblies verified using formal methods. Low-power verification strategy also launched.
May 21, 2013
Spec-TRACER addresses stringent design reporting demands in safety-critical markets, some of which are moving into the mainstream.
May 14, 2013
Jasper Design Automation's modular concept moves into a hot area in SoC design to verify specs are still met after power management circuitry is inserted.
April 10, 2013
The device modeling specialist has integrated its new NanoSpice simulator with existing capture and analysis tools in a broad design-for-yield package.
April 8, 2013
FinFETs, ever proliferating verification, 3DIC, security and more feature on our guide to some of the most intriguing panels at DAC 2013.
February 21, 2013
Some conservative decisions were important parts of AMD's design strategy for the 28nm core that's just been specified in PlayStation 4
November 16, 2012
Mentor's Stephen Pateras explains how the proposed IJTAG standard speeds IP test by replacing time-consuming custom and ad hoc methodologies.
November 12, 2012
HAPS-70 boards launch with latest Xilinx chips, high-speed time-domain multiplexing and Synopsys' take on the debug crunch.