Low-power logic for steampunks

By Chris Edwards |  2 Comments  |  Posted: June 13, 2012
Topics/Categories: Conferences, Blog - EDA, IP  |  Tags: , , , , ,

“Why are we looking at mechanical switches?” asked Professor Tsu-Jae King Liu of the University of California at Berkeley as she started a session at the VLSI Technology Symposium on Tuesday on low-power devices. “We looked at mechanical switches in the early 1800s and we moved away from them.”

But things are changing as CMOS runs out of steam – submicron mechanical switches are not being developed to satisfy some steampunk fantasy: “With Moore’s Law we have been able to improve the speed of computing and have lower power. But a large part of the market is going to grow in very, very low power devices that could be embedded in our environment and within us,” she explained. “Energy efficiency is going to be very important. Ideally for low power, you would lower the supply voltage.”

The trouble is that as you wind down the supply voltage, the cycle time increases and the contribution to overall power consumption from leakage increases. “There will be a fundamental energy limit for any CMOS technology,” said King Liu. “That limit exists because of the of the off-state leakage current. A mechanical switch, on the other hand has zero current when it is switched off.”

The basic MEMS switch consists of a bendable bar connected to the source with a gate underneath the middle of the bar such that, when a charge is applied, electrostatic forces pull the free end of the bar onto the drain. As no current flows until you reach the critical voltage, the MEMS relay has a subthreshold slope that is practically zero, way beyond the thermally controlled 60mV/decade limit of CMOS. It is the ultimate steep subthreshold slope device.

If it’s so good, why aren’t these things in high volume already? One is manufacturing complexity: there are not any MEMS processes optimized for integrating milions of these switches at sufficiently low scale. The one TI developed for its mirror-based projector technology is perhaps the closest. There are other issues before you get to that point: reliability and speed.

Conceptually, you would expect the bar to snap after millions of up-down movements over its life. In practice, that is not the main cause of failure. “The displacement is usually very small. So fatigue is not an issue,” said King Liu. “Endurance is limited by diffusion at the contact. The relay contact heats up and, eventually, the atoms move so much that the device fails: it welds shut. A low load capacitance helps reduce this diffusion, so that it is possible to reach a trillion cycles.”

King Liu argued that for low duty-cycle applications, such as wireless sensor nodes that have circuits spend 99 per cent of their time doing nothing, the limit of a trillion cycles can still yield a ten-year operating lifetime.

Speed is another handicap for relay-based logic but not necessarily an obstacle to these low-speed sensors.

“The optimal design is quite different from a CMOS circuit,” said King Liu, where a lot of the delay is down to the time it takes to drive a capacitive load. “With CMOS, to minimize the delay between the input and output signal becoming valid, you want to distribute the logic across devices. For a relay, the switching speed is much, much slower. So you would like to minimize the mechanical delay rather than the RC delay. You need fewer relays than CMOS transistors for the same logic function.”

A good technique to improve the operating clock speed, King Liu explained, is to flatten the logic. This has been approach by the Berkeley team by developing a more complex basic switch in which the signal and its complement – derived using different bias conditions – are present in the same core device.

The use of complementary signals also points to a device that’s highly suited to some forms of asynchronous logic that, themselves, rely on the presence of data signals and their complements.

The result, claimed King Liu, is a technology that offers a tenfold reduction in energy consumption versus CMOS. “If you are willing to use parallelism, you can get throughput comparable to that of CMOS.”

Work is continuing to reduce the operating voltage of the relays to obtain greater energy savings when the gates are switching. The silicon germanium beams do not react well to thinning but the Berkeley team has found using bilayer constructions can maintain stability in very thin cantilevers.

The core transistor is bigger than CMOS, and will remain that way. “We think the minimum feature size is 50F2,” said King Liu, but she said that adding more signals to the core switch made it possible to build gates such as a dual-function AND/NAND using just one mechanical switch. “The relay device is larger than a transistor but you need fewer of them.”

2 Responses to Low-power logic for steampunks

  1. Cor on June 15, 2012

    In addition it is also possible to create a flipflop or memory element with a single switch. Such switch will use stiction at the contact (=drain) to keep it down after the gate has been activated. It will also need a gate at the other side to overcome the stiction and release the memory. The concept is already used by two companiies to build non-volatile memories.

  2. Tsu-Jae King Liu on June 21, 2012

    Thanks, Chris, for this nice report! I would to clarify a few points:
    1) Mechanical switches were used in the early 1900s (not 1800s): the first general purpose digital computer was the Z3 comprising 2000 relays – see http://en.wikipedia.org/wiki/Z3_(computer)
    2) We have found that relays designed for logic applications (vs. RF switching applications) should be able to achieve endurance exceeding 1 quadrillion on/off cycles [H. Kam et al., IEDM 2009]. This is adequate for 10 yr operation at 1% activity and 100 MHz switching frequency (= clock frequency for an optimally designed relay logic chip).
    3) The layout area of a relay (~50xFxF, where F is the minimum feature size) will be larger than that of a CMOSFET (~32xFxF); as you noted, since an optimally designed relay logic circuit comprises far fewer switches than an optimally designed CMOS logic circuit, the layout area required for the relay implementation can be comparable to or less than the CMOSFET implementation.

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