Xilinx says it has made the first public release of its Vivado Design Suite – the reworked design environment for its sub-40mn programmable-logic devices that is based more heavily on concepts from the custom-IC world than its existing ISE toolset.
The 2012.2 release can be downloaded by any customers in warranty with an ISE Design Suite license. This release, says the FPGA maker, is the first half of a two-phase rollout. The 2012.2 concentrates on hardware-design tools, including high-level synthesis, RTL synthesis with support for SystemVerilog design and verification. Vivado uses a new place-and-route tool and a timing engine that accepts SDC constraints.
Xilinx claims complex designs produced using Vivado provide an average improvement in performance of approximately 15 per cent – roughly equivalent to an FPGA speed grade boost – over one implemented using ISE.
ISE users can also use one element of Vivado in their existing flow: the high-level synthesis tool is available for DSP Edition and System Edition users who are in warranty. The tool will take algorithms expressed in C, C++ or SystemC and generate RTL.