Imperas Software has put together a suite of tools to verify that custom RISC-V processor cores remain compatible with the common infrastructure behind the open-source instruction set.
As RISC-V makes it possible for SoC team to develop a custom processor without having to take out an architectural licence, that design team also takes on the risks and responsibility that comes with the extra complexity of processor verification. Due to the wide range of configuration options within the RISC-V specifications, verification calls for extensive set-up. Imperas reckons the increasing popularity of open-source IP is also contributing to the growth in teams undertaking verification as an in-coming quality inspection as part of initial phase of an SoC project, plus the design option to modify or extend the base core functionality will depend on a working design-verification framework from the start.
The company put together ImperasDV to try to reduce the setup time and streamline processor verification using UVM and SystemVerilog. The key components are a golden reference model for RISC-V processors, integrated test bench components, test suites, and professional support and training. The golden reference model supports the latest extensions for cryptoprocessing, and vector and signal-processing operations.
The verification environment supports the RISC-V Verification Interface (RVVI) standard, which is intended to ease integration between customer RTL, reference model and the testbench. The integration supports step-and-compare verification for complex superscalar pipelines that may be able to run multiple hardware threads and issue and complete instructions out of order.
The product supports multiple options for popular instruction stream generators (ISGs), including Google’s open-source RISCV-DV, the FORCE-RISCV open source ISG maintained by the OpenHW Group, and Valtrix Systems’ STING test generator. The latter supports pre-integrated Imperas RISC-V reference models to generate portable bare-metal programs containing self-checking architecturally-correct test stimulus