Why design data integrity matters from cell design to tapeout. These techniques will help ensure your validation process is as comprehensive as possible.
Insights from research into reliability at Imec led to self-learning chips, security technologies, and finFET biosensors.
3D integration technology has split into a number of different approaches, each of which brings a different combination of benefits in terms of performance.
A new technique has been developed to catch potential new lithography issues when little design data is available for incoming nodes.
How to get the best PV results by reducing computational demands; handling data more efficiently and exploiting parallelization.
John Ferguson reviews the key capital metrics you need to review when deciding whether to move to a new process.
How to address increasingly complex patterning issues and debug them efficiently as design moves toward 12 and 10nm.
Diagnosis-driven yield analysis identifies the cause of systematic yield loss to speed the ramp-to-volume on new processes and improve yield on mature ones.
An alphabet soup of AI, HPC, 5G and the IoT has finally seeded creation of a design infrastructure for silicon photonics.
Pattern-based design/technology co-optimization (DTCO) estimates lithographic difficulty during the early stages of a new process technology node.
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