Make it easier to exercise state machines with SystemVerilog
How the use of declarative, constraint-based descriptions can help you focus command sequences on areas of interest.
constraints
An easier way to make reliability rules and checks more consistent
Learn how XML-based constraints can standardize rule development and use with coding examples for the Calibre PERC reliability platform.
Formal fundamentals: what’s hiding behind your constraints
Effective formal verification demands striking a careful balance in the use of constraints – too many slows things down, but too few may let bugs slip through.
A new path for analog design constraints verification
Traditional techniques are being challenged by shortening design cycles and the effects of later process nodes.
20nm timing analysis – a practical and scalable approach
Using hierarchy and improved constraints management to accelerate static timing analysis at 20nm and below.
Reducing PCB design cycle by 60%
The PCB design team on Alcatel Shanghai Bell’s recently introduced A7510 Media Gateway product was given only seven weeks to complete its task against an original estimate of 13 weeks. The article describes how the team added new members and adopted a concurrent design strategy to not merely meet but beat the tightened deadline. Specific […]
Learning the value of preparation and simulation by OSMOSIS
OSMOSIS is a super-fast optical switch developed through the Advanced Simulation and Computing program. The article describes the strategies adopted by the IBM team charged with designing the Central Scheduler board for the project. The design was of a far greater complexity than the team had previously encountered, and as a result, developed new pre-preparation […]
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