Foundry

June 9, 2020
place and route in design automated hotspot fixing

How to achieve fast, automated, sign-off verification of DFM hotspot fixes in P&R

A collaboration between GlobalFoundries and Mentor has resulted in an innovative in-design fixing strategy across markets such as IoT, mobile, RF, graphics and networking.
Article  |  Topics: EDA - DFM, IC Implementation, Verification  |  Tags: , , , , , , ,   |  Organizations: ,
May 7, 2020
CMP simulation dummy fill featured image

Keep chip designs on the level with CMP simulation and dummy fill optimization

This case study shows how rising CMP simulation quality can be leveraged to detect the position and type of planarity hotspots before manufacture and verify the planarity of a layout.
Article  |  Topics: EDA - DFM  |  Tags: , , ,   |  Organizations: ,
April 24, 2020
Ron Press is the technology enablement director of the Tessent product family at Mentor, A Siemens Business. He is a member of the International Test Conference (ITC) Steering Committee, a Golden Core member of the IEEE Computer Society, and a Senior Member of the IEEE.

How to gain a competitive edge with advanced DFT

Learn how the latest design for test innovations deliver efficiency and profitability across the design flow.
January 19, 2020

How to build your GDS to OASIS conversion flow

Master the three prerequisites of format translation and chose the right one from the various translation strategies.
Article  |  Topics: EDA - DFM  |  Tags: , , , ,   |  Organizations: , ,
May 21, 2019
Calibre node introduction feature - May 2019

Preparing for success at the next node with Calibre

How Mentor develops and works with partners to prepare each version of its Calibre DFM platform to be ready for the introduction of each new process node.
December 31, 2018
MBH featured image

Enhanced model-based hinting may be the edge you need below 20nm

A detailed dive into how MBH strategies for litho hotspots have been enhanced to deal with double patterning at 20nm and below.
Article  |  Topics: EDA - DFM  |  Tags: , , , , , ,   |  Organizations: , , , ,
November 20, 2018
HDAP_FeaturedImage

Adding system-level, post-layout electrical analysis to HDAP design and verification

Adoption of high-density advanced packaging (HDAP) needs tools and supports to build designers' confidence in the emerging technology.
Article  |  Topics: EDA - IC Implementation, Verification  |  Tags: , , , , , ,   |  Organizations: , ,
September 11, 2018
Gandharv Bhatara is the product marketing manager for the Calibre OPC/RET products at Mentor, a Siemens Business.

EUV’s arrival demands a new resolution enhancement flow

Gandharv Bhatara looks at how the OPC and RET elements of Calibre are getting ready for the EUV age.
Expert Insight  |  Topics: EDA - DFM, - EDA Topics  |  Tags: , , , , , , ,   |  Organizations: , ,
February 1, 2018
Design space exploration feature

Design space exploration finds hotspots during early process development

A new technique has been developed to catch potential new lithography issues when little design data is available for incoming nodes.
November 24, 2017
John Ferguson is the Director of Marketing for Calibre DRC Applications at Mentor, a Siemens Business, in Wilsonville, Oregon, with extensive experience in physical design verification. He holds a BS degree in Physics from McGill University, an MS in Applied Physics from the University of Massachusetts, and a PhD in Electrical Engineering from the Oregon Graduate Institute of Science and Technology.

Assessing the true cost of node transitions

John Ferguson reviews the key capital metrics you need to review when deciding whether to move to a new process.

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