Calibre

December 9, 2020
Calibre Interactive feature intro image

Addressing challenges in IC verification configuration

Invocation GUIs play an important role in delivering efficient verification runs. Learn how to take advantage of the features within Calibre Interactive.
Article  |  Topics: EDA - Verification  |  Tags: , ,   |  Organizations: ,
October 16, 2020
Dina Medhat - Mentor

Not using reliability check waivers? You’re wasting valuable time

Reliability rule checks need - and now get - more granular analysis that allows designers to adopt proposed waivers with much greater confidence.
Expert Insight  |  Topics: EDA - DFM  |  Tags: , , , , , ,   |  Organizations:
September 21, 2020
filler cells featim sep20

P&R filler cell insertion slowing you down? Replace it

A physical verification-ready flow can speed project delivery by making your use of filler cells more efficient.
Article  |  Topics: EDA - IC Implementation, Verification  |  Tags: , , , , ,   |  Organizations:
August 25, 2020
Hend Wagieh is the senior product manager for Calibre circuit verification at Mentor, a Siemens Business. Her responsibilities include defining the product roadmap, business strategies, and associated new use models needed to grow the product line and increase market competitiveness for the Calibre nmLVS platform. Hend holds a degree in Electronics and Communication Engineering from Ain Shams University in Cairo, Egypt.

Creating a new paradigm for circuit verification

How Calibre is evolving to address the challenges of LVS verification in early-stage design.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:
August 14, 2020
John Ferguson is the product management director for Calibre DRC applications at Mentor, a Siemens BusinessHe holds a B.Sc. degree in Physics from McGill University, an M.Sc. in Applied Physics from the University of Massachusetts, and a Ph.D. in Electrical Engineering from the Oregon Graduate Institute of Science and Technology.

EDA innovation is the foundation of progress

For physical verification and beyond, each process node requires new thinking, new tools and greater performance.
Expert Insight  |  Topics: EDA - DFM, Verification  |  Tags: , , , , , , , ,   |  Organizations:
June 9, 2020
place and route in design automated hotspot fixing

How to achieve fast, automated, sign-off verification of DFM hotspot fixes in P&R

A collaboration between GlobalFoundries and Mentor has resulted in an innovative in-design fixing strategy across markets such as IoT, mobile, RF, graphics and networking.
April 14, 2020
Power ground check featim

How automated power/ground short checks slash time during implementation

Early detection using design integrity checks during implementation from abstract LEF/DEF inputs can deliver major efficiencies.
Article  |  Topics: EDA - IC Implementation, Verification  |  Tags: , , , , , , , , ,   |  Organizations:
February 14, 2020
P2P-Feb20-featuredimage

A better way to debug P2P results

P2P (point-to-point) resistance is fundamental to IC reliability verification. Handle it more efficiently with detailed, automated path layout analysis.
October 9, 2019
Dina Medhat - Mentor

An easier way to make reliability rules and checks more consistent

Learn how XML-based constraints can standardize rule development and use with coding examples for the Calibre PERC reliability platform.
July 27, 2019

Optimize your database with duplicate data deletion

Whether you use OASIS or GDSII, unwanted duplicate cells can make their way into the final SoC database. Learn how to remove them.
Article  |  Topics: EDA - DFM  |  Tags: , , , , , , ,   |  Organizations:

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