Addressing challenges in IC verification configuration
Invocation GUIs play an important role in delivering efficient verification runs. Learn how to take advantage of the features within Calibre Interactive.
Calibre
Not using reliability check waivers? You’re wasting valuable time
Reliability rule checks need - and now get - more granular analysis that allows designers to adopt proposed waivers with much greater confidence.
P&R filler cell insertion slowing you down? Replace it
A physical verification-ready flow can speed project delivery by making your use of filler cells more efficient.
Creating a new paradigm for circuit verification
How Calibre is evolving to address the challenges of LVS verification in early-stage design.
EDA innovation is the foundation of progress
For physical verification and beyond, each process node requires new thinking, new tools and greater performance.
How to achieve fast, automated, sign-off verification of DFM hotspot fixes in P&R
A collaboration between GlobalFoundries and Mentor has resulted in an innovative in-design fixing strategy across markets such as IoT, mobile, RF, graphics and networking.
How automated power/ground short checks slash time during implementation
Early detection using design integrity checks during implementation from abstract LEF/DEF inputs can deliver major efficiencies.
A better way to debug P2P results
P2P (point-to-point) resistance is fundamental to IC reliability verification. Handle it more efficiently with detailed, automated path layout analysis.
An easier way to make reliability rules and checks more consistent
Learn how XML-based constraints can standardize rule development and use with coding examples for the Calibre PERC reliability platform.
Optimize your database with duplicate data deletion
Whether you use OASIS or GDSII, unwanted duplicate cells can make their way into the final SoC database. Learn how to remove them.
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