Calibre

October 6, 2022
3D-IC Stack LVS Connectivity

Building confidence and flexibility in 3D-IC system level design

3D-IC presents major connectivity challenges in maintaining a golden netlist and managing necessary exceptions. Learn how to manage them.
Article  |  Topics: EDA - DFM, Verification  |  Tags: , , , , ,   |  Organizations:
May 10, 2022
Coordinate-based checks feature

A quick and easy way to calculate P2P resistance and current density

Coordinate-based checking provides a streamlined way to verify designs around ESD before full-chip runs without the need for custom checks.
November 12, 2021
Pre-processing and post-processing techniques for verification

How to optimize productivity and accuracy in IC design and verification flows

Pre- and post-processing EDA techniques help streamline design rule checks and delivery efficient waivers to speed design and debug.
July 20, 2021
Credit: laborotorio linux

Making sense of cloud EDA

How to carry out a sensible analysis of cloud EDA's potential, so you get the right tools and computational resources to deliver increasingly complex designs.
Article  |  Topics: EDA - DFM  |  Tags: , , , , ,   |  Organizations:
June 21, 2021
LEF abstract vs GDS

Out-of-sync data issues in parallel design flows need automated design integrity checks

Overcome problems created by mismatches between library exchange format (LEF) and GDS or OASIS representations to avoid design delays.
Article  |  Topics: EDA - IC Implementation, Verification  |  Tags: , , , , , ,   |  Organizations:
December 9, 2020
Calibre Interactive feature intro image

Addressing challenges in IC verification configuration

Invocation GUIs play an important role in delivering efficient verification runs. Learn how to take advantage of the features within Calibre Interactive.
Article  |  Topics: EDA - Verification  |  Tags: , ,   |  Organizations: ,
October 16, 2020
Dina Medhat - Mentor

Not using reliability check waivers? You’re wasting valuable time

Reliability rule checks need - and now get - more granular analysis that allows designers to adopt proposed waivers with much greater confidence.
Expert Insight  |  Topics: EDA - DFM  |  Tags: , , , , , ,   |  Organizations:
September 21, 2020
filler cells featim sep20

P&R filler cell insertion slowing you down? Replace it

A physical verification-ready flow can speed project delivery by making your use of filler cells more efficient.
Article  |  Topics: EDA - IC Implementation, Verification  |  Tags: , , , , ,   |  Organizations:
August 25, 2020
Hend Wagieh is the senior product manager for Calibre circuit verification at Mentor, a Siemens Business. Her responsibilities include defining the product roadmap, business strategies, and associated new use models needed to grow the product line and increase market competitiveness for the Calibre nmLVS platform. Hend holds a degree in Electronics and Communication Engineering from Ain Shams University in Cairo, Egypt.

Creating a new paradigm for circuit verification

How Calibre is evolving to address the challenges of LVS verification in early-stage design.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:
August 14, 2020
John Ferguson is the product management director for Calibre DRC applications at Mentor, a Siemens BusinessHe holds a B.Sc. degree in Physics from McGill University, an M.Sc. in Applied Physics from the University of Massachusetts, and a Ph.D. in Electrical Engineering from the Oregon Graduate Institute of Science and Technology.

EDA innovation is the foundation of progress

For physical verification and beyond, each process node requires new thinking, new tools and greater performance.
Expert Insight  |  Topics: EDA - DFM, Verification  |  Tags: , , , , , , , ,   |  Organizations:

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